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ADV7122 Folha de dados(PDF) 11 Page - Analog Devices |
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ADV7122 Folha de dados(HTML) 11 Page - Analog Devices |
11 / 12 page ADV7121/ADV7122 –11– REV. B Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 8). Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV7121/ADV7122 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reduce ing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three terminal voltage regulator. Digital Signal Interconnect The digital signal lines to the ADV7121/ADV7122 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the ana- log power plane. Due to the high clock rates used, long clock lines to the ADV7121/ADV7122 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV7121/ADV7122 should be located as close as possible to the output connectors thus minimizing noise pickup and re- flections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7121/ADV7122 so as to minimize reflections. Additional information on PCB design is available in an appli- cation note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from Analog Devices, publication no. E1309–15–10/89. Figure 8. ADV7121/ADV7122 Typical Connection Diagram and Component List GND FS ADJUST IOR IOG IOB GROUND ADV7121/ADV7122 C3 0.1 µF C5 0.1 µF Z1 (AD589) R1 75 Ω R2 75 Ω R3 75 Ω C1 33 µF C2 10 µF COMP C6 0.1 µF ANALOG POWER PLANE L2 (FERRITE BEAD) R0 R9 G0 G9 B0 B9 CLOCK SYNC* BLANK* RGB VIDEO OUTPUT VIDEO DATA INPUTS VIDEO CONTROL INPUTS ANALOG GROUND PLANE C4 0.1 µF L1 (FERRITE BEAD) *SYNC and BLANK FUNCTIONS ARE NOT PROVIDED ON THE ADV7121. V AA V REF +5V (V CC) R SET 560 Ω COMPONENT C1 C2 C3, C4, C5, C6 L1, L2 R1, R2, R3 R SET Z1 DESCRIPTION 33 µF TANTALUM CAPACITOR 10 µF TANTALUM 0.1 µF CERAMIC CAPACITOR FERRITE BEAD 75 Ω 1% METAL FILM RESISTOR 1.235V VOLTAGE REFERENCE 560 Ω 1% METAL FILM RESISTOR VENDOR PART NUMBER FAIR-RITE 274300111 OR MURATA BL01/02/03 DALE CMF-55C ANALOG DEVICES AD589JH DALE CMF-55C |
Nº de peça semelhante - ADV7122 |
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Descrição semelhante - ADV7122 |
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