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ADV7162KS140 Folha de dados(PDF) 4 Page - Analog Devices |
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ADV7162KS140 Folha de dados(HTML) 4 Page - Analog Devices |
4 / 44 page REV. 0 –4– ADV7160/ADV7162 MPU PORT 8,9 Parameter 220 MHz 170 MHz 140 MHz Units Conditions/Comments Version Version Version t19 0 0 0 ns min R/W, C0, C1 to CE Setup Time t20 10 10 10 ns min R/W, C0, C1 to CE Hold Time t21 45 45 45 ns min CE Low Time t22 25 25 25 ns min CE High Time t23 8 5 5 5 ns min CE Asserted to Data-Bus Driven t24 9 45 45 45 ns max CE Asserted to Data Valid t25 9 20 20 20 ns max CE Disabled to Data-Bus Three-Stated t26 9 5 5 5 ns min CE Disabled to Data Invalid t27 20 20 20 ns min Write Data (D0–D9) Setup Time t28 5 5 5 ns min Write Data (D0–D9) Hold Time NOTES General Notes 1TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. Data-Bus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT & SCKOUT ≤ 30 pF. 2 ±5% for all versions 3Temperature range (T MIN to TMAX); 0°C to +70°C. Notes on PIXEL PORT 4Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B, C, D] GREEN [A, B, C, D] BLUE [A, B, C, D] Palette Selects: PS0 [A, B, C, D]; PS1[A, B, C, D] Pixel Controls: SYNC , BLANK, TRISYNC, ODD/EVEN Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT 5 τ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 2:1 multiplexing; τ = CLOCK × 2= 2 × t 1 ns 4:1 multiplexing; τ = CLOCK × 4= 4 × t 1 ns 8:1 multiplexing; τ = CLOCK × 8= 8 × t 1 ns 6These fixed values for Pipeline Delay are valid under conditions where t 10 and τ-t11 are met. If either t10 or τ-t11 are not met, the part will operate but the Pipeline Delay is increased. Notes on ANALOG OUTPUTS 7Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10% and 90% points of full-scale transition. Transition time measured from the 50% point of full scale transition to the output remaining within 2% of the final output value. (Transition time does not include clock and data feedthrough). Notes on MPU PORT 8t 23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V. 9t 25 and t26 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured numbers are then extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the times t 25 and t26, quoted in the Timing Characteristics are the true values for the device and as such are independent of external loading capacitances. Specifications subject to change without notice. 100pF TO OUTPUT PIN ISOURCE ISINK +2.1V Figure 1. Load Circuit for Databus Access and Relinquish Times |
Nº de peça semelhante - ADV7162KS140 |
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Descrição semelhante - ADV7162KS140 |
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