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ADV7178KS Folha de dados(PDF) 10 Page - Analog Devices

Nome de Peças ADV7178KS
Descrição Electrónicos  Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
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ADV7177/ADV7178
–10–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
Input/
No.
Mnemonic
Output
Function
1, 20, 28, 30
VAA
P
+5 V Supply.
2
CLOCK/2
O
Synchronous Clock output signal. Can be either 27 MHz or 13.5 MHz; this
can be controlled by MR32 and MR33 in Mode Register 3.
3–10, 12–14,
P15–P0
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb
37–41
Pixel Port (P15–P0). P0 represents the LSB.
11
OSD_EN
I
Enables OSD input data on the video outputs.
15
HSYNC
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
16
FIELD/
VSYNC
I/O
Dual Function FIELD (Mode 1) and
VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
17
BLANK
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is
Logic Level “0.” This signal is optional.
18
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address.
19, 21, 29, 42
GND
G
Ground Pin.
22
RESET
I
The input resets the on-chip timing generator and sets the ADV7177/ADV7178
into default mode. This is NTSC operation, Timing Slave Mode 0, 8-Bit
Operation, 2
× Composite and S VHS out.
23
SCLOCK
I
MPU Port Serial Interface Clock Input.
24
SDATA
I/O
MPU Port Serial Data Input/Output.
25
COMP
O
Compensation Pin. Connect a 0.1
µF Capacitor from COMP to V
AA.
26
DAC C
O
DAC C Analog Output.
27
DAC B
O
DAC B Analog Output.
31
DAC A
O
DAC A Analog Output.
32
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
33
RSET
I
A 300
Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the Video Signals.
34–36
OSD_0–2
I
On Screen Display Inputs.
43
CLOCK
O
Crystal Oscillator output (to crystal). Leave unconnected if no crystal is used.
44
CLOCK
I
Crystal Oscillator input. If no crystal is used this pin can be driven by an
external TTL Clock source; it requires a stable 27 MHz reference Clock for
standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL)
can be used for square pixel operation.


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