© 2000 Fairchild Semiconductor Corporation

DS009511

www.fairchildsemi.com

April 1988

Revised September 2000

74F273

Octal D-Type Flip-Flop

General Description

The 74F273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered

Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The

device is useful for applications where the true output only

is required and the Clock and Master Reset are common to

all storage elements.

Features

s Ideal buffer for MOS microprocessor or memory

s Eight edge-triggered D-type flip-flops

s Buffered common clock

s Buffered, asynchronous Master Reset

s See 74F377 for clock enable version

s See 74F373 for transparent latch version

s See 74F374 for 3-STATE version

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number

Package Number

Package Description

74F273SC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74F273SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F273PC

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide