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74F382SC Folha de dados(PDF) 2 Page - Fairchild Semiconductor |
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74F382SC Folha de dados(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description Signals applied to the Select inputs S0–S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arith- metic functions for either active HIGH or active LOW oper- ands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 2. The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a HIGH signal on OVR indicates overflow in twos comple- ment operation. Typical delays for Figure 2 are given in Figure 1. Function Select Table H = HIGH Voltage Level L = LOW Voltage Level FIGURE 1. 16-Bit Delay Tabulation FIGURE 2. 16-Bit Ripply Carry ALU Expansion Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL A0–A3 A Operand Inputs 1.0/4.0 20 µA/−2.4 mA B0–B3 B Operand Inputs 1.0/4.0 20 µA/−2.4 mA S0–S2 Function Select Inputs 1.0/1.0 20 µA/−0.6 mA Cn Carry Input 1.0/5.0 20 µA/−3.0 mA Cn + 4 Carry Output 50/33.3 −1 mA/20 mA OVR Overflow Output 50/33.3 −1 mA/20 mA F0–F3 Function Outputs 50/33.3 −1 mA/20 mA Select Operation S0 S1 S2 L L L Clear H L L B Minus A L H L A Minus B HH L A Plus B LL H A ⊕ B HL H A + B LH H AB HHH Preset Path Segment Toward Output F Cn + 4, OVR A1 or B1 to Cn + 4 6.5 ns 6.5 ns Cn to Cn + 4 6.3 ns 6.3 ns Cn to Cn + 4 6.3 ns 6.3 ns Cn to F 8.1 ns — Cn to Cn + 4, OVR — 8.0 ns Total Delay 27.2 ns 27.1 ns |
Nº de peça semelhante - 74F382SC |
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Descrição semelhante - 74F382SC |
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