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74F413PC Folha de dados(PDF) 2 Page - Fairchild Semiconductor |
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74F413PC Folha de dados(HTML) 2 Page - Fairchild Semiconductor |
2 / 5 page www.fairchildsemi.com 2 Functional Description Data Input— Data is entered into the FIFO on D0–D3 inputs. To enter data the Input Ready (IR) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. Simultaneously, data will prop- agate to the second location and continue shifting until it reaches the output stage or a full location. If the memory is full, IR will remain LOW. Data Transfer— Once data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will “bubble” to the front. The tPT parameter defines the time required for the first data to travel from input to the output of a previously empty device. Data Output— Data is read from the O0–O3 outputs. When data is shifted to the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW, the upstream data, pro- vided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. If the FIFO is emptied, OR stays LOW, and O0–O3 remains as before, i.e., data does not change if FIFO is empty. Input Ready and Output Ready— may also be used as status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least tPT) or completely empty (Output Ready stays LOW for at least tPT). Block Diagram |
Nº de peça semelhante - 74F413PC |
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Descrição semelhante - 74F413PC |
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