© 2001 Fairchild Semiconductor Corporation

DS500103

www.fairchildsemi.com

January 2000

Revised October 2001

74LVT16952 • 74LVTH16952

Low Voltage 16-Bit Registered Transceiver

with 3-STATE Outputs

General Description

The LVT16952 and LVTH16952 are 16-bit registered

transceivers. Two 8-bit back to back registers store data

flowing in both directions between two bidirectional buses.

Separate clock, clock enable, and output enable signals

are provided for each register.

The LVTH16952 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

The registered transceiver is designed for low-voltage

TTL interface to a 5V environment.

The LVT16952 and LVTH16952 are fabricated with an

advanced BiCMOS technology to achieve high speed oper-

ation similar to 5V ABT while maintaining low power dissi-

pation.

Features

s Input and output interface capability to systems at

s Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16952)

s Live insertion/extraction permitted

s Power Up/Down high impedance provides glitch-free

bus loading

s Outputs source/sink

−32 mA/+64 mA

s Functionally compatible with the 74 series 16952

s Latch-up conforms to JEDEC JED78

s ESD performance:

Human-body model

> 2000V

Machine model

> 200V

Charged-device model

> 1000V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package Number

Package Description

74LVT16952MEA

(Preliminary)

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16952MTD

(Preliminary)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16952MEA

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVTH16952MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide