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74VCX32500G Folha de dados(PDF) 2 Page - Fairchild Semiconductor |
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74VCX32500G Folha de dados(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Function Table H = HIGH Voltage Level L = LOW Level Voltage X = Immaterial (HIGH or LOW, Inputs may not float) Z = High Impedance Note 2: Output level before the indicated steady-state input conditions were established provided that CP was HIGH before LE went LOW. Note 3: Output level before the indicated steady-state input conditions were established. Logic Diagram Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CP Clock Input I1 - I18 Data Inputs O1 - O18 3-STATE Outputs Inputs Outputs OE LE CP In On H XXX Z LH X L L LH X H H LL ↑ LL LL ↑ HH LL H X O0 (Note 2) LLL X O0 (Note 3) |
Nº de peça semelhante - 74VCX32500G |
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Descrição semelhante - 74VCX32500G |
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