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HCPL-M456 Folha de dados(PDF) 8 Page - AVAGO TECHNOLOGIES LIMITED

Nome de Peças HCPL-M456
Descrição Electrónicos  Small Outline, 5 Lead Intelligent Power Module Optocoupler
Download  14 Pages
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Fabricante Electrônico  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Página de início  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

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IPM Dead Time and Propagation Delay Specifications
The HCPL-M456 includes a Propagation Delay Difference
specification intended to help designers minimize “dead
time”in their power inverter designs. Dead time is the time
period during which both the high and low side power
transistors (Q1 and Q2 in Figure 22) are off. Any overlap in
Q1 and Q2 conduction will result in large currents flowing
through the power devices between the high and low
voltage motor rails.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the characteristics of the IPM IGBT gate drive
circuit can be analyzed in the same way) it is important
to know the minimum and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay specifications, preferably
over the desired operating temperature range.
The limiting case of zero dead time occurs when the input
to Q1 turns off at the same time that the input to Q2 turns
on. This case determines the minimum delay between
LED1 turn-off and LED2 turn-on, which is related to the
worst case optocoupler propagation delay waveforms,
as shown in Figure 23. A minimum dead time of zero is
achieved in Figure 23 when the signal to turn on LED2
is delayed by (tPLH max - tPHL min) from the LED1 turn off.
Note that the propagation delays used to calculate PDD
are taken at equal temperatures since the optocouplers
under consideration are typically mounted in close prox-
imity to each other. (Specifically, tPLHmax and tPHLmin in
the previous equation are not the same as the tPLHmax
and tPHLmin, over the full operating temperature range,
specified in the data sheet.) This delay is the maximum
value for the propagation delay difference specification
which is specified at 370 ns for the HCPL-M456 over an
operating temperature range of -40° C to 100° C.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with
the fastest tPLH and another with the slowest tPHL are in
the same inverter leg. The maximum dead time in this
case becomes the sum of the spread in the tPLH and tPHL
propagation delays as shown in Figure 24. The maximum
dead time is also equivalent to the difference between
the maximum and minimum propagation delay differ-
ence specifications. The maximum dead time (due to the
optocouplers) for the HCPL-M456 is 520 ns (= 370 ns -
(-150 ns)) over an operating temperature range of -40° C
to 100° C.
CMR With The LED Off (CMRH)
A high CMR LED drive circuit must keep the LED off (VF
≤ VF(OFF)) during common mode transients. For example,
during a +dVCM/dt transient in Figure 18, the current
flowing through CLEDN is supplied by the parallel combi-
nation of the LED and series resistor. As long as the voltage
developed across the resistor is less than VF(OFF) the LED
will remain off and no common mode failure will occur.
Even if the LED momentarily turns on, the 100 pF capacitor
from pins 5-4 will keep the output from dipping below the
threshold. The recommended LED drive circuit (Figure 13)
provides about 10 V of margin between the lowest opto-
coupler output voltage and a 3 V IPM threshold during a
15 kV/
Ps transient with VCM=1500 V. Additional margin
can be obtained by adding a diode in parallel with the
resistor, as shown by the dashed line connection in Figure
18, to clamp the voltage across the LED below VF(OFF).
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED off during a +dVCM/dt transient, it is
not desirable for applications requiring ultra high CMRH
performance. Figure 20 is the AC equivalent circuit for
Figure 19 during common mode transients. Essentially
all the current flowing through CLEDN during a +dVCM/dt
transient must be supplied by the LED. CMRH failures can
occur at dv/dt rates where the current through the LED
and CLEDN exceeds the input threshold. Figure 21 is an
alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the off state.


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