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74VHC139MTC Folha de dados(PDF) 1 Page - Fairchild Semiconductor |
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74VHC139MTC Folha de dados(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page November 1992 Revised April 1999 © 1999 Fairchild Semiconductor Corporation DS011521.prf www.fairchildsemi.com 74VHC139 Dual 2-to-4 Decoder/Demultiplexer General Description The VHC139 is an advanced high speed CMOS Dual 2-to- 4 Decoder/Demultiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintain- ing the CMOS low power dissipation. The active LOW enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held HIGH, all four outputs are fixed at a HIGH logic level independent of the other inputs. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: tPD = 5.0 ns (typ) at TA = 25°C s Low power dissipation: ICC = 4 µA (Max.) at TA = 25°C s High noise immunity: VNIH = VNIL = 28% VCC (Min.) s Power down protection is provided on all inputs s Pin and function compatible with 74HC139 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Description Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Order Number Package Number Package Description 74VHC139M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC139MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC139N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Pin Names Description A0, A1 Address Inputs E Enable Inputs O0–O3 Outputs Inputs Outputs E A0 A1 O0 O1 O2 O3 H X X HHHH L LLL H H H L H LH LH H L L HHH L H L HHHHH L |
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