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Functional Description

The VHC175 consists of four edge-triggered D flip-flops

with individual D inputs and Q and Q outputs. The Clock

and Master Reset are common. The four flip-flops will store

the state of their individual D inputs on the LOW-to-HIGH

clock (CP) transition, causing individual Q and Q outputs to

follow. A LOW input on the Master Reset (MR) will force all

Q outputs LOW and Q outputs HIGH independent of Clock

or Data inputs. The VHC175 is useful for general logic

applications where a common Master Reset and Clock are

acceptable.

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs

Outputs

LL

H

HH

L