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ADM3485EAR-REEL7 Folha de dados(PDF) 6 Page - Analog Devices |
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ADM3485EAR-REEL7 Folha de dados(HTML) 6 Page - Analog Devices |
6 / 16 page ADM3485E Rev. D | Page 6 of 16 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS RO 1 RE 2 DE 3 DI 4 VCC 8 B 7 A 6 GND 5 ADM3485E TOP VIEW (Not to Scale) Figure 2. SOIC_N Pin Configuration (R-8) Table 5. Pin Function Descriptions Mnemonic Pin Number Description RO 1 Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low. RE 2 Receiver Output Enable. With RE low, the receiver output (RO) is enabled. With RE high, the output goes into a high impedance state. If RE is high and DE is low, the ADM3485E enters a shutdown state. DE 3 Driver Output Enable. A high level enables the driver differential outputs A and B. A low level places it in a high impedance state. DI 4 Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, while a logic high on DI forces A high and B low. GND 5 Ground Connection, 0 V. A 6 Noninverting Receiver Input A/Driver Output A. B 7 Inverting Receiver Input B/Driver Output B. VCC 8 Power Supply, 3.3 V ± 0.3 V. |
Nº de peça semelhante - ADM3485EAR-REEL7 |
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Descrição semelhante - ADM3485EAR-REEL7 |
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