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DM74LS109A Folha de dados(PDF) 3 Page - Fairchild Semiconductor

Nome de Peças DM74LS109A
Descrição Electrónicos  Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

DM74LS109A Folha de dados(HTML) 3 Page - Fairchild Semiconductor

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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 7: All typicals are at VCC = 5V, TA = 25°C.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 9: ICC is measured with all outputs OPEN, with CLOCK grounded after setting the Q and Q outputs HIGH in turn.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 7)
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
−1.5
V
VOH
HIGH Level
VCC = Min, IOH = Max
2.7
3.4
V
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
0.35
0.5
Output Voltage
VIL = Max, VIH = Min
V
IOL = 4 mA, VCC = Min
0.25
0.4
II
Input Current @ Max
VCC = Max
J, K
0.1
Input Voltage
VI = 7V
Clock
0.1
mA
Preset
0.2
Clear
0.2
IIH
HIGH Level
VCC = Max
J,K
20
Input Current
VI = 2.7V
Clock
20
µA
Preset
40
Clear
40
IIL
LOW Level
VCC = Max
J, K
−0.4
Input Current
VI = 0.4V
Clock
−0.4
mA
Preset
−0.8
Clear
−0.8
IOS
Short Circuit Output Current
VCC = Max (Note 8)
−20
−100
mA
ICC
Supply Current
VCC = Max (Note 9)
4
8
mA
From (Input)
RL = 2 kΩ
Symbol
Parameter
To (Output)
CL = 15 pF
CL = 50 pF
Units
MinMax
MinMax
fMAX
Maximum Clock Frequency
25
20
MHz
tPLH
Propagation Delay Time
Clock to
25
35
ns
LOW-to-HIGH Level Output
Q or Q
tPHL
Propagation Delay Time
Clock to
30
35
ns
HIGH-to-LOW Level Output
Q or Q
tPLH
Propagation Delay Time
Clear
25
35
ns
LOW-to-HIGH Level Output
to Q
tPHL
Propagation Delay Time
Clear
30
35
ns
HIGH-to-LOW Level Output
to Q
tPLH
Propagation Delay Time
Preset
25
35
ns
LOW-to-HIGH Level Output
to Q
tPHL
Propagation Delay Time
Preset
30
35
ns
HIGH-to-LOW Level Output
to Q


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