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AD5531BRUZ-REEL71 Folha de dados(PDF) 6 Page - Analog Devices |
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AD5531BRUZ-REEL71 Folha de dados(HTML) 6 Page - Analog Devices |
6 / 20 page AD5530/AD5531 Rev. B | Page 6 of 20 DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter Limit at TMIN, TMAX Unit Description 1 , 2 , 3 fMAX 2 MHz max SCLK frequency t1 500 ns min SCLK cycle time t2 200 ns min SCLK low time t3 200 ns min SCLK high time t4 50 ns min SYNC to SCLK falling edge setup time t5 40 ns min SCLK falling edge to SYNC rising edge t6 50 ns min Min SYNC high time t7 40 ns min Data setup time t8 15 ns min Data hold time t12 50 ns min CLR pulse width t13 130 ns min SCLK falling edge to SDO valid t14 50 ns max SCLK falling edge to SDO invalid t15 50 ns min RBEN to SCLK falling edge setup time t16 50 ns min RBEN hold time t17 100 ns min RBEN falling edge to SDO valid 1 Guaranteed by design, not subject to production test. 2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 SDO; RPULLUP = 5 kΩ, CL = 15 pF SCLK SYNC SDIN SDO (DAISY- CHAINING) RBEN SDO (READBACK) MSB DB15 DB14 DB11 DB0 DB15 DB11 DB0 LSB MSB LSB MSB LSB RB0 RB13 00 t1 t3 t2 t5 t4 t6 t7 t8 t13 t14 t15 t16 t13 t14 t17 Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode |
Nº de peça semelhante - AD5531BRUZ-REEL71 |
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Descrição semelhante - AD5531BRUZ-REEL71 |
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