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LM2842 Folha de dados(PDF) 2 Page - Texas Instruments |
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LM2842 Folha de dados(HTML) 2 Page - Texas Instruments |
2 / 19 page CB 1 2 3 4 5 6 LM2840/1/2 GND FB SW PIN 1 ID VIN SHDN LM2841, LM2842 SNVS540H – MARCH 2009 – REVISED APRIL 2013 www.ti.com Connection Diagram Top View Figure 1. SOT 6 Lead See Package Number DDC (R-PDSO-G6) PIN DESCRIPTIONS Pin Name Function 1 CB SW FET gate bias voltage. Connect CBOOT cap between CB and SW. 2 GND Ground connection. Feedback pin: Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2)). Resistors should be 3 FB in the 100-10K range to avoid input bias errors. 4 SHDN Logic level shutdown input. Pull to GND to disable the device and pull high to enable the device. If this function is not used tie to VIN or leave open. 5 VIN Power input voltage pin: 4.5V to 42V normal operating range. 6 SW Power FET output: Connect to inductor, diode, and CBOOT cap. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM2841 LM2842 |
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