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FM34W02ULZ Folha de dados(PDF) 9 Page - Fairchild Semiconductor |
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FM34W02ULZ Folha de dados(HTML) 9 Page - Fairchild Semiconductor |
9 / 12 page 9 www.fairchildsemi.com FM34W02U Rev. A.1 S T O P Bus Activity: Master SDA Line DATA n + 15 DATA n + 1 DATA n BYTE ADDRESS (n) A C K S T A R T SLAVE ADDRESS A C K A C K A C K A C K S T O P A C K DATA A C K A C K S T A R T WORD ADDRESS SLAVE ADDRESS Bus Activity: Master SDA Line S T O P Bus Activity: Master SDA Line Bus Activity: DEVICE ADDRESS DATA DON'T CARE DON'T CARE BYTE ADDRESS A C K S T A R T SLAVE ADDRESS A C K A C K Write Protect Scheme (Continued) Byte Write (Figure 5). Page Write (Figure 6). WP Register Write (Figure 7). Read Operations Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read. CURRENT ADDRESS READ Internally the FM34W02U contains an address counter that main- tains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the FM34W02U issues an acknowledge and transmits the data byte. The master will not acknowledge the transfer but does generate a stop condition, and therefore the FM34W02U discontinues transmission. Refer to Figure 8 for the sequence of address, acknowledge and data transfer. RANDOM READ Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition, slave address, R/W bit set to zero, and then the word address to be read. After the slave word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowl- edge from the FM34W02U and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the FM34W02U discontinues trans- mission. Refer to Figure 9 for the address, acknowledge and data transfer sequence. SEQUENTIAL READ Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The FM34W02U continues to output data for each acknowl- edge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter 'rolls over' and the FM34W02U continues to output data for each acknowledge received. Refer to Figure 10 for the address, acknowledge, and data transfer sequence. |
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