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FM25C160B Folha de dados(PDF) 2 Page - Cypress Semiconductor |
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FM25C160B Folha de dados(HTML) 2 Page - Cypress Semiconductor |
2 / 14 page FM25C160B - 16Kb 5V SPI F-RAM Document Number: 001-84472 Rev. *A Page 2 of 14 Instruction Decode Clock Generator Control Logic Write Protect Instruction Register Address Register Counter 256 x 64 FRAM Array 11 Data I/O Register 8 Nonvolatile Status Register 3 WP CS HOLD SCK SO SI Figure 1. Block Diagram Pin Description Pin Name I/O Pin Description /CS Input Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. SCK Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 20 MHz and may be interrupted at any time. /HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. /WP Input Write Protect: This active low pin prevents write operations to the status register. This is critical since other write protection features are controlled through the status register. A complete explanation of write protection is provided on page 6. *Note that the function of /WP is different from the FM25160. SI Input Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * SI may be connected to SO for a single pin data interface. SO Output Serial Output. SO is the data output pin. It is driven actively during a read and remains tri-state at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * SO may be connected to SI for a single pin data interface. VDD Supply Supply Voltage. 5V VSS Supply Ground |
Nº de peça semelhante - FM25C160B_13 |
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Descrição semelhante - FM25C160B_13 |
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