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FM25H20-DG Folha de dados(PDF) 3 Page - Cypress Semiconductor

Nome de Peças FM25H20-DG
Descrição Electrónicos  2Mb Serial 3V F-RAM Memory
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Fabricante Electrônico  CYPRESS [Cypress Semiconductor]
Página de início  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM25H20-DG Folha de dados(HTML) 3 Page - Cypress Semiconductor

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FM25H20 - 2Mb SPI FRAM
Document Number: 001-85935 Rev. *A
Page 3 of 16
Overview
The FM25H20 is a serial F-RAM memory. The
memory array is logically organized as 262,144 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to Serial Flash. The major
differences between the FM25H20 and a Serial Flash
with the same pinout are the F-RAM‟s superior write
performance, very high endurance, and lower power
consumption.
Memory Architecture
When accessing the FM25H20, the user addresses
256K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a three-
byte address. The complete address of 18-bits
specifies each byte address uniquely.
Most functions of the FM25H20 either are controlled
by the SPI interface or are handled automatically by
on-board circuitry. The access time for memory
operation is essentially zero, beyond the time needed
for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike Serial
Flash, it is not necessary to poll the device for a ready
condition since writes occur at bus speed. So, by the
time a new bus transaction can be shifted into the
device, a write operation will be complete. This is
explained in more detail in the interface section.
Users expect several obvious system benefits from
the FM25H20 due to its fast write cycle and high
endurance as compared to Serial Flash. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than Serial Flash
since it is completed quickly. By contrast, Serial
Flash requiring milliseconds to write is vulnerable to
noise during much of the cycle.
Serial Peripheral Interface – SPI Bus
The FM25H20 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to
40MHz. This high-speed serial bus provides high
performance
serial
communication
to
a
host
microcontroller.
Many common
microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25H20 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25H20 devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25H20 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 3 shows a configuration that uses
only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25H20 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /S, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25H20 supports only modes 0 and 3. Figure 4
shows the required signal relationships for modes 0
and 3.
For both modes, data is clocked into the
FM25H20 on the rising edge of C and data is
expected on the first rising edge after /S goes active.
If the clock starts from a high state, it will fall prior to
the first data transfer in order to create the first rising
edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/S is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /S must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.


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