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FM28V202 Folha de dados(PDF) 9 Page - Cypress Semiconductor |
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FM28V202 Folha de dados(HTML) 9 Page - Cypress Semiconductor |
9 / 18 page FM28V202 - 128Kx16 F-RAM Document Number: 001-86602 Rev. ** Page 9 of 18 ENDURANCE The FM28V202 is capable of being accessed at least 10 14 times – reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A16-A2 and column addresses by A1-A0. The array is organized as 32K rows of 4-words each. The entire row is internally accessed once whether a single 16- bit word or all four words are read or written. Each word in the row is counted only once in an endurance calculation. The user may choose to write CPU instructions and run them from a certain address space. The table below shows endurance calculations for 256-byte repeating loop, which includes a starting address, 3 page mode accesses, and a CE precharge. The number of bus clocks needed to complete a 4-word transaction is 4+1 at lower bus speeds, but 5+2 at 33MHz due to initial read latency and an extra clock to satisfy the device’s precharge timing constraint t PC. The entire loop causes each byte to experience only one endurance cycle. F-RAM read and write endurance is virtually unlimited even at 33MHz system bus clock rate. Table 3. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop Bus Freq (MHz) Bus Cycle Time (ns) 256-byte Transaction Time ( s) Endurance Cycles/sec. Endurance Cycles/year Years to Reach 10 14 Cycles 33 30 10.56 94,690 2.98 x 10 12 33.5 25 40 12.8 78,125 2.46 x 10 12 40.6 10 100 28.8 34,720 1.09 x 10 12 91.7 5 200 57.6 17,360 5.47 x 10 11 182.8 |
Nº de peça semelhante - FM28V202 |
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Descrição semelhante - FM28V202 |
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