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Os motores de busca de Datasheet de Componentes eletrônicos |
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MC145483ENR2 Folha de dados(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC145483ENR2 Folha de dados(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 24 page  PIN DESCRIPTIONS POWER SUPPLY VDD Positive Power Supply (Pin 6) This is the most positive power supply and is typically con- nected to + 3 V. This pin should be decoupled to VSS with a 0.1 µF ceramic capacitor. VSS Negative Power Supply (Pin 15) This is the most negative power supply and is typically connected to 0 V. VAG Analog Ground Output (Pin 20) This output pin provides a mid–supply analog ground. This pin should be decoupled to VSS with a 0.01 µF ceramic ca- pacitor. All analog signal processing within this device is ref- erenced to this pin. If the audio signals to be processed are referenced to VSS, then special precautions must be utilized to avoid noise between VSS and the VAG pin. Refer to the ap- plications information in this document for more information. The VAG pin becomes high impedance when this device is in the powered–down mode. VAG Ref Analog Ground Reference Bypass (Pin 1) This pin is used to capacitively bypass the on–chip circuit- ry that generates the mid–supply voltage for the VAG output pin. This pin should be bypassed to VSS with a 0.1 µF ceram- ic capacitor using short, low inductance traces. The VAG Ref pin is only used for generating the reference voltage for the VAG pin. Nothing is to be connected to this pin in addition to the bypass capacitor. All analog signal processing within this device is referenced to the VAG pin. If the audio signals to be processed are referenced to VSS, then special precautions must be utilized to avoid noise between VSS and the VAG pin. Refer to the applications information in this document for more information. When this device is in the powered–down mode, the VAG Ref pin is pulled to the VDD power supply with a non–linear, high–impedance circuit. CONTROL HB Transmit High–Pass Filter Bypass (Pin 16) This pin selects whether the transmit high–pass filter will be used or bypassed, which allows frequencies below 200 Hz to appear at the input of the ADC to be digitized. This high–pass filter is a third order filter for attenuating power line frequencies, typically 50/60 Hz. A logic low selects this filter. A logic high deselects or bypasses this filter. When the filter is bypassed, the transmit frequency response extends down to dc. PDI Power–Down Input (Pin 10) This pin puts the device into a low power dissipation mode when a logic 0 is applied. When this device is powered down, all of the clocks are gated off and all bias currents are turned off, which causes RO–, PO–, PO+, TG, VAG, and DT to be- come high impedance. The device will operate normally when a logic 1 is applied to this pin. The device goes through a power–up sequence when this pin is taken to a logic 1 state, which prevents the DT PCM output from going low im- pedance for at least two FST cycles. The VAG and VAG Ref circuits and the signal processing filters must settle out be- fore the DT PCM output or the RO– receive analog output will represent a valid analog signal. ANALOG INTERFACE TI + Transmit Analog Input (Non–Inverting) (Pin 19) This is the non–inverting input of the transmit input gain setting operational amplifier. This pin accommodates a differ- ential to single–ended circuit for the input gain setting op amp. This allows input signals that are referenced to the VSS pin to be level shifted to the VAG pin with minimum noise. This pin may be connected to the VAG pin for an inverting amplifier configuration if the input signal is already refer- enced to the VAG pin. The common mode range of the TI+ and TI– pins is from 1.2 V, to VDD minus 1.2 V. This is an FET gate input. The TI+ pin also serves as a digital input control for the transmit input multiplexer. Connecting the TI+ pin to VDD will place this amplifier’s output (TG) into a high–impedance state, and selects the TG pin to serve as a high–impedance input to the transmit filter. Connecting the TI+ pin to VSS will also place this amplifier’s output (TG) into a high–impedance state, and selects the TI– pin to serve as a high–impedance input to the transmit filter. TI– Transmit Analog Input (Inverting) (Pin 18) This is the inverting input of the transmit gain setting op- erational amplifier. Gain setting resistors are usually con- nected from this pin to TG and from this pin to the analog signal source. The common mode range of the TI+ and TI– pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input. The TI– pin also serves as one of the transmit input mulit- plexer pins when the TI+ pin is connected to VSS. When TI+ is connected to VDD, this pin is ignored. See the pin descrip- tions for the TI+ and the TG pins for more information. TG Transmit Gain (Pin 17) This is the output of the transmit gain setting operational amplifier and the input to the transmit band–pass filter. This op amp is capable of driving a 2 k Ω load. Connecting the TI+ pin to VDD will place the TG pin into a high–impedance state, and selects the TG pin to serve as a high–impedance input to the transmit filter. All signals at this pin are referenced to the VAG pin. When TI+ is connected to VSS, this pin is ignored. See the pin descriptions for TI+ and TI– pins for more in- formation. This pin is high impedance when the device is in the powered–down mode. RO– Receive Analog Output (Inverting) (Pin 2) This is the inverting output of the receive smoothing filter from the digital–to–analog converter. This output is capable of driving a 2 k Ω load to 0.886 V peak referenced to the VAG pin. If the device is operated half–channel with the FST pin clocking and FSR pin held low, the receive filter input will be Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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Descrição semelhante - MC145483ENR2 |
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