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AD7846JPZ Folha de dados(PDF) 7 Page - Analog Devices |
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AD7846JPZ Folha de dados(HTML) 7 Page - Analog Devices |
7 / 24 page AD7846 Rev. G | Page 7 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD7846 DB11 DB12 DB13 DB14 DB15 DB2 DB1 DB0 VDD VCC VSS VOUT VREF+ VREF– RIN DB10 DB9 DB8 DB7 DB6 DGND DB3 DB4 DB5 LDAC R/W CS CLR Figure 7. PDIP Pin Configuration 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 12 13 14 15 16 17 18 LDAC CLR CS R/W DGND DB6 VOUT VREF+ VREF– RIN VSS DB15 DB14 AD7846 VCC Figure 8. CERDIP Pin Configuration Table 5. Pin Function Descriptions Pin Mnemonic Description 1 to 3 DB2 to DB0 Data I/Os. DB0 is LSB. 4 VDD Positive Supply for Analog Circuitry. This is +15 V nominal. 5 VOUT DAC Output Voltage. 6 RIN Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6. 7 VREF+ VREF+ Input. The DAC is specified for VREF+ = +5 V. 8 VREF− VREF− Input. For unipolar operation connect VREF− to 0 V, and for bipolar operation connect it to −5 V. The device is specified for both conditions. 9 VSS Negative Supply for the Analog Circuitry. This is −15 V nominal. 10 to 19 DB15 to DB6 Data I/Os. DB15 is MSB. 20 DGND Ground for Digital Circuitry. 21 VCC Positive Supply for Digital Circuitry. This is +5 V nominal. 22 R/W R/W Input. This pin can be used to load data to the DAC or to read back the DAC latch contents. 23 CS Chip Select Input. This pin selects the device. 24 CLR Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7. 25 LDAC Asynchronous Load Input to DAC. 26 to 28 DB5 to DB3 Data I/Os. Table 6. Output Voltage Ranges Output Range VREF+ VREF− RIN 0 V to +5 V +5 V 0 V VOUT 0 V to +10 V +5 V 0 V 0 V +5 V to −5 V +5 V −5 V VOUT +5 V to −5 V +5 V 0 V +5 V +10 V to −10 V +5 V −5 V 0 V |
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