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LM1881 Folha de dados(PDF) 2 Page - Texas Instruments

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Nome de Peças LM1881
Descrição Electrónicos  AC Coupled Composite input Signal
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

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LM1881
SNLS384F – FEBRUARY 1995 – REVISED MARCH 2013
www.ti.com
Absolute Maximum Ratings
(1) (2)
Supply Voltage
13.2V
Input Voltage
3 VP-P (VCC = 5V)
6 VP-P (VCC ≥ 8V)
Output Sink Currents; Pins, 1, 3, 5
5 mA
Output Sink Current; Pin 7
2 mA
Package Dissipation (3)
1100 mW
Storage Temperature Range
−65°C to +150°C
ESD Susceptibility (4)
2 kV
ESD Susceptibility (5)
200 V
Soldering Information
PDIP Package (10 sec.)
260°C
SOIC Package
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2)
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3)
For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a
package thermal resistance of 110°C/W, junction to ambient.
(4)
ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 k
Ω resistor”.
(5)
Machine Model, 220 pF – 240 pF discharged through all pins.
Electrical Characteristics LM1881
VCC = 5V; RSET = 680 kΩ; TA = 0°C to +70°C by correlation with 100% electrical testing at TA=25°C
Parameter
Conditions
Min
Typ (1)
Max
Units
Supply Current
Outputs at
VCC = 5V
5.2
10
mA
Logic 1
VCC = 12V
5.5
12
DC Input Voltage
Pin 2
1.3
1.5
1.8
V
Input Threshold Voltage
(2)
55
70
85
mV
Input Discharge Current
Pin 2; VIN = 2V
6
11
16
µA
Input Clamp Charge Current
Pin 2; VIN = 1V
0.2
0.8
mA
RSET Pin Reference Voltage
Pin 6; (3)
1.10
1.22
1.35
V
Composite Sync. & Vertical
IOUT = 40 µA;
VCC = 5V
4.0
4.5
V
Outputs
Logic 1
VCC = 12V
11.0
IOUT = 1.6 mA
VCC = 5V
2.4
3.6
V
Logic 1
VCC = 12V
10.0
Burst Gate & Odd/Even Outputs
IOUT = 40 µA;
VCC = 5V
4.0
4.5
V
Logic 1
VCC = 12V
11.0
Composite Sync. Output
IOUT = −1.6 mA; Logic 0; Pin 1
0.2
0.8
V
Vertical Sync. Output
IOUT = −1.6 mA; Logic 0; Pin 3
0.2
0.8
V
Burst Gate Output
IOUT = −1.6 mA; Logic 0; Pin 5
0.2
0.8
V
Odd/Even Output
IOUT = −1.6 mA; Logic 0; Pin 7
0.2
0.8
V
Vertical Sync Width
190
230
300
µs
Burst Gate Width
2.7 k
Ω from Pin 5 to VCC
2.5
4
4.7
µs
Vertical Default Time
(4)
32
65
90
µs
(1)
Typicals are at TJ = 25°C and represent the most likely parametric norm.
(2)
Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
(3)
Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the RSET pin (Pin
6).
(4)
Delay time between the start of vertical sync (at input) and the vertical output pulse.
2
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