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74LVC1G125FZ4-7 Folha de dados(PDF) 6 Page - Diodes Incorporated |
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74LVC1G125FZ4-7 Folha de dados(HTML) 6 Page - Diodes Incorporated |
6 / 12 page 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT 74LVC1G125 Document number: DS32202 Rev. 6 - 2 6 of 12 www.diodes.com February 2012 © Diodes Incorporated Parameter Measurement Information RL RL CL (see Note A) From Output Under Test VLOAD Open GND S1 TEST S1 tPLH/tPHL Open tPLZ/tPZL Vload tPHZ/tPZH GND VCC Inputs VM VLOAD CL RL V ∆ VI tr/tf 1.8V±0.15V VCC ≤2ns VCC/2 2 X VCC 30pF 1K Ω 0.15V 2.5V±0.2V VCC ≤2ns VCC/2 2 X VCC 30pF 500 Ω 0.15V 2.7V 2.7V ≤2.5ns 1.5V 6V 50pF 500 Ω 0.3V 3.3V±0.3V 3V ≤2.5ns 1.5V 6V 50pF 500 Ω 0.3V 5V±0.5V VCC ≤2.5ns VCC/2 2 X VCC 50pF 500 Ω 0.3V Voltage Waveform Pulse Duration Voltage Waveform Enable and Disable Times Low and High Level Enabling Voltage Waveform Propagation Delay Times Inverting and Non Inverting Outputs Figure 1. Load Circuit and Voltage Waveforms Notes: A. Includes test lead and test apparatus capacitance. B. All pulses are supplied at pulse repetition rate ≤ 10 MHz. C. Inputs are measured separately one transition per measurement. D. tPLZ and tPHZ are the same as tdis. E. tPZL and tPZH are the same as tEN. F. tPLH and tPHL are the same as tPD. |
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