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SI5324C-C-GM Folha de dados(PDF) 7 Page - Silicon Laboratories |
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SI5324C-C-GM Folha de dados(HTML) 7 Page - Silicon Laboratories |
7 / 72 page Si5324 Rev. 1.0 7 Output Drive Current (CMOS driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally) CKOIO ICMOS[1:0] = 11 VDD =1.8 V —7.5 — mA ICMOS[1:0] = 10 VDD =1.8 V —5.5 — mA ICMOS[1:0] = 01 VDD =1.8 V —3.5 — mA ICMOS[1:0] = 00 VDD =1.8 V —1.75 — mA ICMOS[1:0] = 11 VDD =3.3 V —32 — mA ICMOS[1:0] = 10 VDD =3.3 V —24 — mA ICMOS[1:0] = 01 VDD =3.3 V —16 — mA ICMOS[1:0] = 00 VDD =3.3 V —8 — mA 2-Level LVCMOS Input Pins Input Voltage Low VIL VDD =1.71V — — 0.5 V VDD =2.25V — — 0.7 V VDD =2.97V — — 0.8 V Input Voltage High VIH VDD =1.89V 1.4 — — V VDD =2.25V 1.8 — — V VDD =3.63V 2.5 — — V Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. |
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Descrição semelhante - SI5324C-C-GM |
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