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AD654JR Folha de dados(PDF) 10 Page - Analog Devices |
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AD654JR Folha de dados(HTML) 10 Page - Analog Devices |
10 / 12 page AD654 –10– REV. 8 7 6 5 1 2 3 4 AD654 68k 1k VIN (0V TO 1V) CT 100pF +5V 0.1 F 0.1 F RT = 1k + – A J270 J270 Q1 Q2 MINIMUM DISTANCE +15V V1 68k V2 10 F 10 F + 5.9k 1% ( 2) R7 8.2 MINIMUM DISTANCE 0.1 F 10 F D –5V V3 A3-a A3-b 18 470pF A3-c A3-d V4 A3 = 74LS86 A2 LM360 D 10 F 0.1 F +15V Figure 13. 2 MHz, Frequency Doubling V/F OPERATION AT HIGHER OUTPUT FREQUENCIES Operation of the AD654 via the conventional output (Pins 1 and 2) is speed limited to approximately 500 kHz for reasons of TTL logic compatibility. Although the output stage may become speed limited, the multivibrator core itself is able to oscillate to 1 MHz or more. The designer may take advantage of this feature in order to operate the device at frequencies in excess of 500 kHz. Figure 13 illustrates this with a circuit offering 2 MHz full scale. In this circuit the AD654 is operated at a full scale (FS) of 1 mA, with a CT of 100 pF. This achieves a basic device FS frequency of 1 MHz across CT. The P channel JFETs, Q1 and Q2, buffer the differential timing capacitor waveforms to a low impedance level where the push-pull signal is then ac coupled to the high speed comparator A2. Hysteresis is used, via R7, for nonambiguous switching and to eliminate the oscillations which would other- wise occur at low frequencies. The net result of this is a very high speed circuit which does not compromise the AD654 dynamic range. This is a result of the FET buffers typically having only a few pA of bias current. The high end dynamic range is limited, however, by parasitic package and layout capacitances in shunt with CT, as well as those from each node to ac ground. Minimizing the lead length between A2–6/A2–7 and Q1/Q2 in PC layout will help. A ground plane will also help stability. Figure 14 shows the waveforms V1–V4 found at the respective points shown in Figure 13. The output of the comparator is a complementary square wave at 1 MHz FS. Unlike pulse train output V/F converters, each half-cycle of the AD654 output conveys information about the input. Thus it is possible to count edges, rather than full cycles of the output, and double the effective output frequency. The XOR gate following A2 acts as an edge detector producing a short pulse for each input state transition. This effectively doubles the V/F FS frequency to 2 MHz. The final result is a 1 V full-scale input V/F with a 2 MHz full-scale output capability; typical nonlinearity is 0.5%. 100 90 10 0% 500ns 2V 5V 2V 5V 2V 0 2V 0 5V 0 5V 0 V1 V2 V3 V4 Figure 14. Waveforms of 2 MHz Frequency Doubler C |
Nº de peça semelhante - AD654JR |
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Descrição semelhante - AD654JR |
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