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AD7568BPZ-REEL Folha de dados(PDF) 7 Page - Analog Devices |
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AD7568BPZ-REEL Folha de dados(HTML) 7 Page - Analog Devices |
7 / 14 page AD7568 –7– Interface Section The AD7568 is a serial input device. Three lines control the se- rial interface, FSIN, CLKIN and SDIN. The timing diagram is shown in Figure 1. When the FSIN input goes low, data appearing on the SDIN line is clocked into the input shift register on each falling edge of CLKIN. When sixteen bits have been received, the register loading is automatically disabled until the next falling edge of FSIN detected. Also, the received data is clocked out on the next rising edge of CLKIN and appears on the SDOUT pin. This feature allows several devices to be connected together in a daisy chain fashion. When the sixteen bits have been received in the input shift regis- ter, DB3 (A0) is checked to see if it corresponds to the state of pin A0. If it does, then the word is accepted. Otherwise, it is dis- regarded. This allows the user to address one of two AD7568s in a very simple fashion. DB0 to DB2 of the 16-bit word deter- mine which of the eight DAC input latches is to be loaded. When the LDAC line goes low, all eight DAC latches in the de- vice are simultaneously loaded with the contents of their respec- tive input latches, and the outputs change accordingly. Bringing the CLR line low resets the DAC latches to all 0s. The input latches are not affected, so that the user can revert to the previous analog output if desired. 16-BIT INPUT SHIFT REGISTER CLKIN SDIN SDOUT FSIN Figure 14. Input Logic 0 –100 –70 –90 –80 –40 –60 –50 –30 –20 –10 103 10 4 10 5 106 107 V = +5V T = +25 °C V = 20V pk-pk OP AMP = AD713 DD A IN DAC LOADED WITH ALL 1s DAC LOADED WITH ALL 0s Figure 12. Multiplying Frequency Response vs. Digital Code GENERAL DESCRIPTION D/A Section The AD7568 contains eight 12-bit current-output D/A convert- ers. A simplified circuit diagram for one of the D/A converters is shown in Figure 13. A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A, B and C. The remaining 10 bits of the data word drive the switches S0 to S9 in a standard R–2R ladder configuration. Each of the switches A to C steers 1/4 of the total reference cur- rent with the remaining current passing through the R–2R section. Each DAC in the device has separate VREF, IOUT1, IOUT2 and RFB pins. This makes the device extremely versatile and allows DACs in the same device to be configured differently. When an output amplifier is connected in the standard configu- ration of Figure 15, the output voltage is given by: VOUT = –D•VREF where D is the fractional representation of the digital word loaded to the DAC. Thus, in the AD7568, D can be set from 0 to 4095/4096. VREF 2R 2R 2R 2R 2R 2R 2R CB A S9 S8 S9 RFB I OUT1 I OUT2 R R R R/2 SHOWN FOR ALL 1s ON DAC Figure 13. Simplified D/A Circuit Diagram REV. C |
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