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AD8062 Folha de dados(PDF) 10 Page - Analog Devices |
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AD8062 Folha de dados(HTML) 10 Page - Analog Devices |
10 / 24 page AD5545/AD5555 Data Sheet Rev. G | Page 10 of 24 SERIAL DATA INTERFACE The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK) serial data interface for single channel update operation. With Table 7 as an example (AD5545), users can tie LDAC low and RS high, and then pull CS low for an 18-bit duration. New serial data is then clocked into the serial-input register in an 18- bit data-word format with the MSB bit loaded first. Table 8 defines the truth table for the AD5555. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK. For the AD5545, only the last 18-bits clocked into the serial register are interrogated when the CS pin is strobed high, transferring the serial register data to the DAC register and updating the output. If the applied microcontroller outputs serial data in different lengths than the AD5545, such as 8-bit bytes, three right justified data bytes can be written to the AD5545. The AD5545 ignores the six MSB and recognizes the 18 LSB as valid data. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register and updates the output; during the CS strobe, the CLK should not be toggled. If users want to program each channel separately but update them simultaneously, program LDAC and RS high initially, then pull CS low for an 18-bit duration and program DAC A with the proper address and data bits. CS is then pulled high to latch data to the DAC A register. At this time, the output is not updated. To load DAC B data, pull CS low for an 18-bit duration and program DAC B with the proper address and data, then pull CS high to latch data to the DAC B register. Finally, pull LDAC low and then high to update both the DAC A and DAC B outputs simultaneously. Table 6 shows that each DAC A and DAC B can be individually loaded with a new data value. In addition, a common new data value can be loaded into both DACs simultaneously by setting Bit A1 = A0 = high. This command enables the parallel combination of both DACs, with IOUTA and IOUTB tied together, to act as one DAC with significant improved noise performance. ESD Protection Circuits All logic input pins contain back-biased ESD protection Zeners connected to digital ground (DGND) and VDD as shown in Figure 19. VDD 02918- 0- 007 5k Ω DGND DIGITAL INPUTS Figure 19. Equivalent ESD Protection Circuits Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1 MSB LSB Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1 MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 6. Address Decode A1 A0 DAC Decoded 0 0 None 0 1 DAC A 1 0 DAC B 1 1 DAC A and DAC B |
Nº de peça semelhante - AD8062 |
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Descrição semelhante - AD8062 |
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