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R1Q2A7209AB Folha de dados(PDF) 20 Page - Renesas Technology Corp |
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R1Q2A7209AB Folha de dados(HTML) 20 Page - Renesas Technology Corp |
20 / 39 page R1QHA72 / R1QLA72 Series Rev. 0.11 : 2013.01.15 PAGE:20 Common Leakage Currents & Output Voltage Parameter Symbol Min Max Unit Test condition Notes Input leakage current I LI −22 μA10 Output leakage current I LO −55 μA11 Output high voltage V OH (Low) V DDQ − 0.2 V DDQ V|I OH| ≤ 0.1 mA 8, 9 V OH V DDQ/2 − 0.12 V DDQ/2 + 0.12 V Note 6 8, 9 Output low voltage V OL (Low) V SS 0.2 V I OL ≤ 0.1 mA 8, 9 V OL V DDQ/2 − 0.12 V DDQ/2 + 0.12 V Note 7 8, 9 Notes: 1. All inputs (except ZQ, V REF) are held at either VIH or VIL. 2. I OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents (I DD) are measured at 100% bus utilization. IDD of QDR family is current of device with 100% write and 100% read cycle. I DD of DDR family is current of device with 100% write cycle (if I DD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)). 4. All address / data inputs are static at either V IN > VIH or VIN < VIL. 5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. ) 6. Outputs are impedance-controlled. |I OH| = (VDDQ/2)/(RQ/5) for values of 175 Ω≤ RQ ≤ 350 Ω. 7. Outputs are impedance-controlled. I OL = (VDDQ/2)/(RQ/5) for values of 175 Ω≤ RQ ≤ 350 Ω. 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 10. 0 ≤ V IN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec. 11. 0 ≤ V OUT ≤ VDDQ (except TDO ball), output disabled. R10DS0173EJ0011 |
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Descrição semelhante - R1Q2A7209AB |
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