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DAC5682 Folha de dados(PDF) 2 Page - Texas Instruments |
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DAC5682 Folha de dados(HTML) 2 Page - Texas Instruments |
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2 / 49 page  GC5330 GC5337 SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (Continued) The CFR block reduces the peak-to-average ratio (PAR) of the digital transmit signals, such as those used in third-generation (3G) code division multiple access (CDMA) and orthogonal frequency-division multiple-access (OFDMA) applications. The DPD path with a 310-MHz DPD clock can be configured to support one antenna at 62 MHz, two antennas at 62 MHz each, or four antennas at 31 MHz each, all with an associated 5 × DPD expansion bandwidth. The GC533x DPD processor reduces power amplifier (PA) nonlinearity, e.g., as measured by adjacent-channel leakage ratio (ACLR), by over 20 dB. By reducing the PAR of the digital signal and the PA nonlinearity, the operational efficiency of follow-on power amplifiers can be substantially improved. A higher DPD bandwidth is possible with reduced DPD performance. Several architectures that provide performance and cost optimization are listed in Table 1 Table 1. Sample Configurations for GC5330 {GC5337} Figure TX Antenna DPD Bandwidth ET Support Feedback RX Antenna Other 2 typical at 250 Lower-cost 2-antenna Figure 1 2-62 {74} MHz 310 {370} MHz Subsampled real Msps, up to 4 at solution 250 Msps 2 at 250Msps, 4 Full-rate real up to 2-antenna solution with Figure 2 2-62 {74} MHz 310 {370} MHz with lower-rate RX 1Gsps full-rate real feedback ADC 2 at 250Msps, 4 2-antenna solution with Subsampled Figure 3 2-62 {74} MHz 310 {370} MHz with lower-rate RX complex feedback, lower complex ADC subsampling ratio 2 at 250Msps, 4 2-antenna solution, with 2-envelope Full-rate real up to Figure 4 2-62 {74} MHz 310 {370} MHz with lower-rate RX envelope tracking with tracking 1Gsps ADC full-rate real feedback 4 at 250Msps, 8 Lower-cost 4 antenna Figure 5 4-31 {37} MHz 155 {185} MHz Subsampled real with lower-rate RX solution ADC 2 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): GC5330 GC5337 |
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