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TPL5000 Folha de dados(PDF) 8 Page - Texas Instruments

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Nome de Peças TPL5000
Descrição Electrónicos  TPL5000 Nano Power Programmable Timer with Watchdog Functionality
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

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TPL5000
SNAS628A – JULY 2013 – REVISED JULY 2013
www.ti.com
APPLICATION INFORMATION
The TPL5000 is a long-term timer with a watchdog feature, for low power applications. The TPL5000 is designed
for use in interrupt-driven applications and provides selectable timing from 1s to 64s. An additional supervisor
feature is achieved through interfacing the TPL5000 to a power management IC.
Configuration and Interface
The time interval between 2 adjacent WAKE pulses (or 2 adjacent RSTn pulses or RSTn and WAKE pulses) is
selectable through 3 digital input pins (D0, D1, D2). These pins can be strapped to either VDD (1) or GND (0).
Eight possible time delays can be selected, as shown in Table 2.
Table 2. Timer Delay Period
D2
D1
D0
Time (s)
Factor N
0
0
0
1
26
0
0
1
2
27
0
1
0
4
28
0
1
1
8
29
1
0
0
10
10*26
1
0
1
16
210
1
1
0
32
211
1
1
1
64
212
Overview of the Timing Signals: WAKE, RSTn, TCAL and DONE
Figure 4 shows the timing of WAKE, RSTn, and TCAL with respect to DONE. The frame, A, shows a typical
sequence after the PGOOD, low to high, transition. As soon as PGOOD is high, the internal oscillator is powered
ON. At the end of the delay period (tDP), a reset signal (RSTn), followed by a calibration pulse, TCAL, is sent out.
The calibration pulse starts after a half period of the internal oscillator from the falling edge of the reset, and lasts
one internal oscillator period.
The frame, B, shows a standard sequence. A "DONE" signal has been received in the previous delay period, so
at the end of the next delay period, a "WAKE", followed by a calibration pulse, is sent out. The WAKE signal
stays high for 2 internal oscillator periods. The calibration pulse starts after a half period of the internal oscillator
from the rising edge of the WAKE signal, and lasts one internal oscillator period. In this frame, the TPL5000
receives a "DONE" signal before the end of the delay period.
The frame, C, still shows a standard sequence, but in this case, the TPL5000 receives the DONE signal when
both WAKE and TCAL pulses are still high. As soon as the TPL5000 recognizes the DONE resets the counter
and puts WAKE and TCAL in the default condition (both signal low).
The frame, D, shows a typical PGOOD, high to low transition. As soon as PGOOD is low, the internal oscillator is
powered OFF and the digital output pins, TCAL, RSTn, and WAKE, are asynchronously reset by the falling edge
of the PGOOD signal, such that TCAL and WAKE reset at low logical values, while RSTn resets at a high logical
value.
8
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