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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AD5629R Folha de dados(PDF) 11 Page - Analog Devices |
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AD5629R Folha de dados(HTML) 11 Page - Analog Devices |
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11 / 32 page  Data Sheet AD5629R/AD5669R Rev. B | Page 11 of 32 Table 6. Pin Function Descriptions Pin No. LFCSP TSSOP WLCSP Mnemonic Description 15 1 B2 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. 16 2 A4 A0 Address Input. Sets the least significant bit of the 7-bit slave address. 1 3 B3 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 2 4 B4 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 5 B1 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 4 6 C4 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. 5 7 C2 VOUTG Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. 6 8 D3 VREFIN/VREFOUT The AD5629R/AD5669R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. 7 9 D2 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero scale, midscale, or full scale. The default setting clears the output to 0 V. 8 10 C3 VOUTH Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. 9 11 C1 VOUTF Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. 10 12 D4 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 11 13 D1 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 12 14 A1 GND Ground Reference Point for All Circuitry on the Parts. 13 15 A3 SDA Serial Data Input. This is used in conjunction with the SCL line to clock data into or out of the 32-bit input shift register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 14 16 A4 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 32-bit input shift register. 17 N/A N/A Exposed Pad (EPAD) The exposed pad must be tied to GND. |
Nº de peça semelhante - AD5629R |
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Descrição semelhante - AD5629R |
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