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SI3050 Folha de dados(PDF) 11 Page - Silicon Laboratories |
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SI3050 Folha de dados(HTML) 11 Page - Silicon Laboratories |
11 / 112 page Si3050 + Si3018/19 Rev. 1.31 11 Figure 3. SPI Timing Diagram Table 7. Switching Characteristics—Serial Peripheral Interface (VIO = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade, CL = 20 pF) Parameter* Symbol Test Conditions Min Typ Max Unit Cycle Time SCLK tc 61.03 — — ns Rise Time, SCLK tr — — 25 ns Fall Time, SCLK tf — — 25 ns Delay Time, SCLK Fall to SDO Active td1 — — 20 ns Delay Time, SCLK Fall to SDO Transition td2 — — 20 ns Delay Time, CS Rise to SDO Tri-state td3 — — 20 ns Setup Time, CS to SCLK Fall tsu1 25 — — ns Hold Time, SCLK to CS Rise th1 20 — — ns Setup Time, SDI to SCLK Rise tsu2 25 — — ns Hold Time, SCLK Rise to SDI Transition th2 20 — — ns Delay time between chip selects tcs 220 — — ns Propagation Delay, SDI to SDITHRU — 6 — ns *Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH =VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. SDO SDI SCLK t su1 t su2 t h2 t d2 t d1 t d3 t h1 CS t f t r t c t cs |
Nº de peça semelhante - SI3050 |
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Descrição semelhante - SI3050 |
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