AD7453BRT-REEL7 datasheet(11/20 Pages) AD

Nome de Peças	AD7453BRT-REEL7

Descrição Electrónicos	Pseudo Differential, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23

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Fabricante Electrônico	AD [Analog Devices]

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AD7453

Rev. B | Page 11 of 20

CIRCUIT INFORMATION

The AD7453 is a 12-bit, low power, single-supply, successive

approximation analog-to-digital converter (ADC) with a

pseudo differential analog input. It operates with a single 2.7 V

to 5.25 V power supply and is capable of throughput rates up to

555 kSPS when supplied with a 10 MHz SCLK. It requires an

external reference to be applied to the VREF pin.

The AD7453 has an on-chip differential track-and-hold

amplifier, a successive approximation (SAR) ADC, and a serial

interface, housed in an 8-lead SOT-23 package. The serial clock

input accesses data from the part and provides the clock source

for the successive approximation ADC. The AD7453 features a

power-down option for reduced power consumption between

conversions. The power-down feature is implemented across the

standard serial interface, as described in the Modes of

Operation section.

CONVERTER OPERATION

The AD7453 is a successive approximation ADC based around

two capacitive DACs. Figure 14 and Figure 15 show simplified

schematics of the ADC in the acquisition and conversion phase,

respectively. The ADC is comprised of control logic, an SAR,

and two capacitive DACs. In Figure 14 (acquisition phase), SW3

is closed and SW1 and SW2 are in Position A, the comparator is

held in a balanced condition, and the sampling capacitor arrays

acquire the differential signal on the input.

VIN+

VIN–

A

B

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

CS

VREF

SW2

B

A

Figure 14. ADC Acquisition Phase

When the ADC starts a conversion (Figure 15), SW3 opens and

SW1 and SW2 move to Position B, causing the comparator to

become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and charge redistribution

DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC’s output code. The output impedances of the sources

driving the VIN+ and VIN– pins must be matched; otherwise the

two inputs have different settling times, resulting in errors.

VIN+

VIN–

A

B

SW1

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

CS

VREF

SW2

B

A

COMPARATOR

Figure 15. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7453 is straight (natural) binary.

The designed code transitions occur at successive LSB values

(i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The

ideal transfer characteristic of the AD7453 is shown in

Figure 16.

000...00

0V

ANALOG INPUT

111...11

000...01

111...00

011...11

1LSB

VREF – 1LSB

1LSB = VREF/4096

111...10

000...10

Figure 16. Ideal Transfer Characteristic

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