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P-TQFP-100-3 Folha de dados(PDF) 6 Page - Infineon Technologies AG

Nome de Peças P-TQFP-100-3
Descrição Electrónicos  2 Channel Serial Optimized Communication Controller for HDLC/PPP
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Fabricante Electrônico  INFINEON [Infineon Technologies AG]
Página de início  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

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PEB 20525
PEF 20525
Table of Contents
Page
Data Sheet
6
2000-09-14
3.2.13.1
NRZ and NRZI Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.13.2
FM0 and FM1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.13.3
Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2.14
Modem Control Signals (RTS, CTS, CD) . . . . . . . . . . . . . . . . . . . . . . . 77
3.2.14.1
RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.2.14.2
Carrier Detect (CD) Receiver Control . . . . . . . . . . . . . . . . . . . . . . . . 78
3.2.15
Local Loop Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.4
External DMA Controller Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.5
Interrupt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.6
General Purpose Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.6.1
GPP Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.6.2
GPP Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4
Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.1
HDLC/SDLC Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.1.0.1
Automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.1.0.2
Address Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.0.3
Address Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.0.4
Address Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.1
HDLC Receive Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.2
Receive Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.3
HDLC Transmit Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.4
Shared Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1.5
One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1.6
Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1.7
CRC Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1.8
Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2
Point-to-Point Protocol (PPP) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.1
Bit Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.2
Octet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.3
Data Transparency in PPP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.3
Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4
Procedural Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4.1
Full-Duplex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.4.2
Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.4.3
Signaling System #7 (SS7) Operation . . . . . . . . . . . . . . . . . . . . . . . . . 103
5
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.1
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.2
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.2.1
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.2.2
Channel Specific SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128


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