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ADCMP608BKSZ-R2 Folha de dados(PDF) 8 Page - Analog Devices |
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ADCMP608BKSZ-R2 Folha de dados(HTML) 8 Page - Analog Devices |
8 / 12 page ADCMP608 Rev. 0 | Page 8 of 12 Q OUTPUT INPUT VOLTAGE 500mV OVERDRIVE 10mV OVERDRIVE DISPERSION VN ± VOS CROSSOVER BIAS POINT Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predeter- mined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. The ADCMP608 slightly elaborates on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V. Figure 10. Propagation Delay—Overdrive Dispersion MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PC board design practice, as discussed in the Q OUTPUT INPUT VOLTAGE 10V/ns 1V/ns DISPERSION VN ± VOS Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscilla- tions are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and PC board. In many applications, chattering is not harmful. Figure 11. Propagation Delay—Slew Rate Dispersion |
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