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TL16C554FNR Folha de dados(PDF) 8 Page - Texas Instruments |
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TL16C554FNR Folha de dados(HTML) 8 Page - Texas Instruments |
8 / 35 page TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS165G − JANUARY 1994 − REVISED MARCH 2006 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 6, 7, and 8) PARAMETER TEST CONDITIONS MIN MAX UNIT td5 Delay time, INTx ↓ to TXx↓ at start 8 24 RCLK cycles td6 Delay time, TXx ↓ at start to INTx↑ See Note 5 8 8 RCLK cycles td7 Delay time, IOW high or low (WR THR) to INTx ↑ See Note 5 16 32 RCLK cycles td8 Delay time, TXx ↓ at start to TXRDY↓ CL = 100 pF 8 RCLK cycles tpd1 Propagation delay time, IOW (WR THR) ↓ to INTx↓ CL = 100 pF 35 ns tpd2 Propagation delay time, IOR (RD IIR) ↑ to INTx↓ CL = 100 pF 30 ns tpd3 Propagation delay time, IOW (WR THR) ↑ to TXRDY↑ CL = 100 pF 50 ns NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time. receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 9 through 13) PARAMETER TEST CONDITIONS MIN MAX UNIT td9 Delay time, stop bit to INTx ↑ or stop bit to RXRDY↓ or read RBR to set interrupt See Note 6 1 RCLK cycle tpd4 Propagation delay time, Read RBR/LSR to INTx ↓/LSR interrupt↓ CL = 100 pF, See Note 7 40 ns tpd5 Propagation delay time, IOR RCLK ↓ to RXRDY↑ See Note 7 30 ns NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts. 7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches. modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage, CL = 100 pF (see Figure 14) PARAMETER MIN MAX UNIT tpd6 Propagation delay time, IOW (WR MCR) ↑ to RTSx, DTRx↑ 50 ns tpd7 Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑ 30 ns tpd8 Propagation delay time, IOR (RD MSR) ↑ to interrupt↓ 35 ns tpd9 Propagation delay time, RIx ↑ to INTx↑ 30 ns |
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Descrição semelhante - TL16C554FNR |
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