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SN74GTLP1395PWRG4 Folha de dados(PDF) 2 Page - Texas Instruments |
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SN74GTLP1395PWRG4 Folha de dados(HTML) 2 Page - Texas Instruments |
2 / 24 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GQN PACKAGE (TOP VIEW) 123 4 A B C D E SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C–JUNE 2001–REVISED JANUARY 2006 This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC.The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74GTLP1395DW SOIC–DW GTLP1395 Tape and reel SN74GTLP1395DWR –40°Cto85°C TSSOP – PW Tape and reel SN74GTLP1395PWR GP395 TVSOP – DGV Tape and reel SN74GTLP1395DGVR GP395 VFBGA – GQN Tape and reel SN74GTLP1395GQNR GP395 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. TERMINAL ASSIGNMENTS 12 3 4 A 1T/C 1Y 1OEBY 2T/C B GND GND 2Y 2OEBY C VCC 1OEAB ERC 1B D GND GND 1A 2B E 2OEAB 2A BIAS VCC VREF 2 |
Nº de peça semelhante - SN74GTLP1395PWRG4 |
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Descrição semelhante - SN74GTLP1395PWRG4 |
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