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AD6655ABCPZ-1251 Folha de dados(PDF) 6 Page - Analog Devices |
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AD6655ABCPZ-1251 Folha de dados(HTML) 6 Page - Analog Devices |
6 / 88 page AD6655 Rev. A | Page 6 of 8 ADC DC SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. Parameter Temperature AD6655BCPZ-125 AD6655BCPZ-150 Unit Min Typ Max Min Typ Max RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.2 ±0.6 % FSR Gain Error Full −4.7 −2.7 −0.8 −5.1 −3.2 −1.0 % FSR MATCHING CHARACTERISTIC Offset Error 25°C ±0.3 ±0.7 ±0.2 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.7 ±0.2 ±0.8 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±18 ±5 ±18 mV Load Regulation @ 1.0 mA Full 7 7 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.85 0.85 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance1 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 1.8 3.6 1.7 1.8 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD2, 3 Full 390 705 440 805 mA IDVDD2, 3 Full 270 320 mA IDRVDD2 (3.3 V CMOS) Full 26 28 mA IDRVDD2 (1.8 V CMOS) Full 13 17 mA IDRVDD2 (1.8 V LVDS) Full 57 57 mA POWER CONSUMPTION DC Input Full 770 810 870 920 mW Sine Wave Input2 (DRVDD = 1.8 V) Full 1215 1395 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 1275 1450 mW Standby Power4 Full 77 77 mW Power-down Power Full 2.5 8 2.5 8 mW 1 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See for the equivalent analog input structure. Figure 11 2 Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately 5 pF loading on each output bit. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND). |
Nº de peça semelhante - AD6655ABCPZ-1251 |
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Descrição semelhante - AD6655ABCPZ-1251 |
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