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AD5501 Folha de dados(PDF) 1 Page - Analog Devices

Nome de Peças AD5501
Descrição Electrónicos  High Voltage, Quad-Channel 12-Bit Voltage Output DAC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD5501 Folha de dados(HTML) 1 Page - Analog Devices

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High Voltage, Quad-Channel
12-Bit Voltage Output DAC
Data Sheet
AD5504
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2009-2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Quad-channel high voltage DAC
12-bit resolution
Pin selectable 30 V or 60 V output range
Integrated precision reference
Low power serial interface with readback capability
Integrated temperature sensor alarm function
Power-on reset
Simultaneous updating via LDAC
Wide operating temperature: −40°C to +105°C
APPLICATIONS
Programmable voltage sources
High voltage LED drivers
Receiver bias in optical communications
GENERAL DESCRIPTION
The AD5504 is a quad-channel, 12-bit, serial input, digital-to-
analog converter with on-chip high voltage output amplifiers
and an integrated precision reference. The DAC output voltage
ranges are programmable via the range select pin (R_SEL). If
R_SEL is held high, the DAC output ranges are 0 V to 30 V. If
R_SEL is held low, the DAC output ranges are 0 V to 60 V. The
on-chip output amplifiers allow an output swing within the
range of AGND + 0.5 V to VDD − 0.5 V.
The AD5504 has a high speed serial interface, which is com-
patible with SPI®-, QSPI™-, MICROWIRE™-, and DSP-interface
standards and can handle clock speeds of up to 16.667 MHz.
FUNCTIONAL BLOCK DIAGRAM
POWER-ON
RESET
DGND
AGND
SDO
SCLK
SDI
SYNC
LDAC
ALARM
CLR R_SEL VLOGIC
VDD
REFERENCE
AD5504
DACA
INPUT
REGISTER
A
DAC
REGISTER
A
VOUTA
+
1713kΩ
122.36kΩ
12
DAC B
INPUT
REGISTER
B
DAC
REGISTER
B
VOUTB
+
1713kΩ
122.36kΩ
12
DAC C
INPUT
REGISTER
C
DAC
REGISTER
C
VOUTC
+
1713kΩ
122.36kΩ
12
DAC D
INPUT
REGISTER
D
DAC
REGISTER
D
VOUTD
+
1713kΩ
122.36kΩ
12
12
TEMPERATURE
SENSOR
POWER-DOWN
CONTROL LOGIC
INPUT
CONTROL
LOGIC
Figure 1.


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