AD7858L datasheet(5/32 Pages) AD

Nome de Peças	AD7858L

Descrição Electrónicos	3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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AD7858/AD7858L

REV. B

–5–

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams for

serial Interface Mode 2. The reading and writing occurs after

conversion in Figure 2, and during conversion in Figure 3. To

attain the maximum sample rate of 100 kHz (AD7858L) or

200 kHz (AD7858), reading and writing must be performed

during conversion as in Figure 3. At least 400 ns acquisition

time must be allowed (the time from the falling edge of BUSY

to the next rising edge of

CONVST) before the next conversion

begins to ensure that the part is settled to the 12-bit level. If the

user does not want to provide the

CONVST signal, the conver-

sion can be initiated in software by writing to the control register.

1.6mA

200 A

IOL

IOH

TO

OUTPUT

CL

100pF

+2.1V

Figure 1. Load Circuit for Digital Output Timing

Specifications

tCONVERT = 4.6 s MAX, 10 s MAX FOR L VERSION

t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V

t1

tCONVERT

t3

t4

t6

t2

t6

t9

t10

t11

t12

t7

t8

THREE-STATE

15

6

16

DB15

DB11

DB0

DB15

DB11

DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

THREE-

STATE

Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

tCONVERT = 4.6 s MAX, 10 s MAX FOR L VERSION

t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V

t1

tCONVERT

t3

t4

t6

t2

t6

t9

t10

t11

t12

t7

t8

THREE-STATE

15

6

16

DB15

DB11

DB0

DB15

DB11

DB0

CONVST (I/P)

BUSY (O/P)

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

THREE-

STATE

Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

Nº de peça semelhante - AD7858L

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