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TPIC1021DG4 Folha de dados(PDF) 9 Page - Texas Instruments |
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TPIC1021DG4 Folha de dados(HTML) 9 Page - Texas Instruments |
9 / 18 page www.ti.com TPIC1021 LIN Physical Interface SLIS113C – OCTOBER 2004 – REVISED JULY 2005 ELECTRICAL CHARACTERISTICS (continued) V SUP = 7 V to 27 V, TA = -40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Pull-down resistor 125 350 800 k Ω IIL Low-level input current EN = 0 V -5 0 5 µA INH PIN Vo DC output voltage Transient voltage -0.3 VSUP+0.3 V IO Ouptut current -50 2 mA Ron On state resistance Between VSUP and INH, INH = 2 mA 25 40 100 Ω drive, Normal or Standby Mode IIKG Leakage current Low Power mode, 0 < INH < VSUP -5 0 5 µA NWake PIN VIL Low-level input voltage (4) -0.3 VSUP-3.3 V VIH High-level input voltage(4) VSUP-1 VSUP+0.3 V Pull-up current NWake = 0 V -40 -10 -4 µA IIKG Leakage current VSUP = NWake -5 0 5 µA THERMAL SHUTDOWN Shutdown junction thermal tempera- 185 °C ture AC CHARACTERISTICS D1 Duty cycle 1(5)(6) THREC(max) = 0.744×VSUP, 0.396 THDOM(max) = 0.581×VSUP, VSUP = 7.0 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 4 D2 Duty cycle 2(5)(6) THREC(max) = 0.284×VSUP, 0.581 THDOM(max) = 0.422×VSUP, VSUP = 7.6 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 4 D3 Duty cycle 3(5)(6) THREC(max) = 0.778×VSUP, 0.417 THDOM(max) = 0.616×VSUP, VSUP = 7.0 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 4 D4 Duty cycle 4(5)(6) THREC(max) = 0.251×VSUP, 0.590 THDOM(max) = 0.389×VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 4 trx_pdr Receiver rising propagation delay RL = 2.4 kΩ, CL = 20 pF, See 6 µs time Figure 4 trx_pdf Receiver falling propagation delay RL = 2.4 kΩ, CL = 20 pF, See 6 µs time Figure 4 trx_sym Symmetry of receiver propagation wrt falling edge, See Figure 4 -2 2 µs delay time (rising edge) tNWake NWake filter time for local wake-up See Figure 4 25 50 100 µs tLINBUS LIN wake-up filter time (dominant See Figure 4 25 50 100 µs time for wake-up via LIN bus) tDST Dominant state timeout(7) See Figure 4 6 9 14 ms (4) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device. (5) Duty cycle = tBUS_rec(min)/ (2×tBIT) (6) Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 k Ω; Load2 = 6.8 nF, 660 Ω; Load3 = 10 nF, 500 Ω. Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is capable of of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details please refer to the SAEJ2602 specification. (7) Dominant state timeout will limit the minimum data rate to 2.4 kbps. 9 |
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