Os motores de busca de Datasheet de Componentes eletrônicos |
|
AM3892BCYG150 Folha de dados(PDF) 2 Page - Texas Instruments |
|
AM3892BCYG150 Folha de dados(HTML) 2 Page - Texas Instruments |
2 / 308 page AM3894 AM3892 SPRS681E – OCTOBER 2010 – REVISED JULY 2012 www.ti.com – USB 2.0 High-/Full-/Low-Speed Host • Three Multichannel Audio Serial Ports – Supports End Points 0-15 – One Six-Serializer Transmit/Receive Port • General Purpose Memory Controller (GPMC) – Two Dual-Serializer Transmit/Receive Ports – 8-/16-bit Multiplexed Address/Data Bus – DIT-Capable For S/PDIF (All Ports) – Up to 6 Chip Selects With up to 256M-Byte • Multichannel Buffered Serial Port (McBSP) Address Space per Chip Select Pin – Transmit/Receive Clocks up to 48 MHz – Glueless Interface to NOR Flash, NAND – Two Clock Zones and Two Serial Data Pins Flash (With BCH and Hamming Error Code – Supports TDM, I2S, and Similar Formats Detection), SRAM and Pseudo-SRAM • Real-Time Clock (RTC) – Error Locator Module (ELM) Outside of – One-Time or Periodic Interrupt Generation GPMC to Provide Up to 16-Bit/512-Bytes • Up to 64 General-Purpose I/O (GPIO) Pins Hardware ECC for NAND • On-Chip ARM® ROM Bootloader (RBL) – Flexible Asynchronous Protocol Control for • Power, Reset, and Clock Management Interface to FPGA, CPLD, ASICs, etc. – SmartReflex™ Technology (Level 2) • Enhanced Direct-Memory-Access (EDMA) – Seven Independent Core Power Domains Controller – Clock Enable/Disable Control For – Four Transfer Controllers Subsystems and Peripherals – 64/8 Independent DMA/QDMA Channels • IEEE-1149.1 (JTAG) and IEEE-1149.7 (cJTAG) • Seven 32-bit General-Purpose Timers Compatible • One System Watchdog Timer • 1031-Pin Pb-Free BGA Package (CYG Suffix), • Three Configurable UART/IrDA/CIR Modules 0.65-mm Ball Pitch – UART0 With Modem Control Signals • Via Channel™ Technology Enables use of 0.8- – Supports up to 3.6864 Mbps UART mm Design Rules – SIR, MIR, FIR (4.0 MBAUD), and CIR • 40-nm CMOS Technology • One 40-MHz Serial Peripheral Interface (SPI) • 3.3-V Single-Ended LVCMOS I/Os (except for With Four Chip-Selects DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN • SD/SDIO serial interface (1-/4-Bit) at 1.8 V) • Dual Inter-Integrated Circuit ( I2C BUS®) Ports 2 Device Summary Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
Nº de peça semelhante - AM3892BCYG150 |
|
Descrição semelhante - AM3892BCYG150 |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |