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CAT25512XI-T2L Folha de dados(PDF) 7 Page - ON Semiconductor |
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CAT25512XI-T2L Folha de dados(HTML) 7 Page - ON Semiconductor |
7 / 16 page CAT25512 http://onsemi.com 7 Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and a data byte as shown in Figure 5. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). Page Write After sending the first data byte to the CAT25512, the host may continue sending data, up to a total of 128 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previously loaded data. Following completion of the write cycle, the CAT25512 is automatically returned to the write disable state. Write Identification Page The additional 128−byte Identification Page (IP) can be written with user data using the same Write commands sequence as used for Page Write to the main memory array (Figure 6). The IPL bit from the Status Register must be set (IPL = 1) using the WRSR instruction, before attempting to write to the IP. The address bits [A15:A7] are Don’t Care and the [A6:A0] bits define the byte address within the Identification Page. In addition, the Byte Address must point to a location outside the protected area defined by the BP1, BP0 bits from the Status Register. When the full memory array is write protected (BP1, BP0 = 1,1), the write instruction to the IP is not accepted and not executed. Also, the write to the IP is not accepted if the LIP bit from the Status Register is set to 1 (the page is locked in Read−only mode). Table 11. BYTE ADDRESS Device Address Significant Bits # Address Clock Pulses Main Memory Array A15 − A0 16 Identification Page A6 − A0 16 Figure 5. Byte WRITE Timing SCK SI SO 00 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 012 345 67 8 OPCODE DATA IN HIGH IMPEDANCE BYTE ADDRESS* 21 22 23 24 25 26 27 28 29 30 31 Dashed Line = mode (1, 1) CS A0 AN 0 * Please check the Byte Address Table (Table 11) Figure 6. Page WRITE Timing SCK SI SO 00 00 0 1 0 BYTE ADDRESS* Data Byte 1 0123 456 78 21 22 23 24−31 32−39 Data Byte N OPCODE 7..1 0 24+(N−1)x8−1 .. 24+(N−1)x8 24+Nx8−1 DATA IN HIGH IMPEDANCE Dashed Line = mode (1, 1) CS AN A0 Data Byte 3 Data Byte 2 0 * Please check the Byte Address Table (Table 11) |
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Descrição semelhante - CAT25512XI-T2L |
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