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TC55VCM416BSGN Folha de dados(PDF) 11 Page - Toshiba Semiconductor |
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TC55VCM416BSGN Folha de dados(HTML) 11 Page - Toshiba Semiconductor |
11 / 18 page TC55VCM416BTGN, TC55VCM416BSGN, TC55VEM416BXGN55 TC55YCM416BTGN, TC55YCM416BSGN, TC55YEM416BXGN70 2005-08-09 11/18 WRITE CYCLE 4 ( , CONTROLLED) Note: ・ Read cycle R/W remains HIGH for the read cycle. ・ Write cycle1 (1) If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (2) If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. Don’t input the same polarity signal as a R/W signal into a OE during the write cycle. ・ Write cycle1 to 4 If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. UB LB Address A0~A19 R/W tWC tAS tWR tWP 1 CE DOUT I/O1~16 VALID DATA IN DIN I/O1~16 tDS tDH Hi-Z Hi-Z tCW CE2 tBW tBE tCOE tODW UB , LB tCW |
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