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AD7248ABR Folha de dados(PDF) 9 Page - Analog Devices |
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AD7248ABR Folha de dados(HTML) 9 Page - Analog Devices |
9 / 16 page AD7245A/AD7248A REV. B –9– The data held in the DAC latch determines the analog output of the converter. Data is latched into the DAC latch on the rising edge of LDAC. This LDAC signal is an asynchronous signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. For example, if LDAC goes LOW while WR is “LOW,” then the LDAC signal must stay LOW for t 7 or longer after WR goes high to ensure correct data is latched through to the output. Table I. AD7245A Truth Table CLR LDAC WR CS Function H L L L Both Latches are Transparent H H H X Both Latches are Latched H H X H Both Latches are Latched H H L L Input Latches Transparent HH g L Input Latches Latched H L H H DAC Latches Transparent H g H H DAC Latches Latched L X X X DAC Latches Loaded with all 0s g H H H DAC Latches Latched with All 0s and Output Remains at 0 V or –5 V g L L L Both Latches are Transparent and Output Follows Input Data H = High State, L = Low State, X = Don’t Care The contents of the DAC latch are reset to all 0s by a low level on the CLR line. With both latches transparent, the CLR line functions like a zero override with the output brought to 0 V in the unipolar mode and –5 V in the bipolar mode for the dura- tion of the CLR pulse. If both latches are latched, a “LOW” pulse on the CLR input latches all 0s into the DAC latch and the output remains at 0 V (or –5 V) after the CLR line has returned “HIGH.” The CLR line can be used to ensure power-up to 0 V on the AD7245A output in unipolar operation and is also use- ful, when used as a zero override, in system calibration cycles. Figure 4 shows the input control logic for the AD7245A and the write cycle timing for the part is shown in Figure 5. LDAC CLR WR CS DAC LATCH INPUT LATCH INPUT DATA Figure 4. AD7245A Input Control Logic CS WR LDAC DATA VALID DATA 5V 0V 5V 0V 5V 0V 5V 0V t3 t4 t5 t6 HIGH IMPEDANCE BUS NOTES 1. SEE TIMING SPECIFICATIONS. 2. ALL INPUT RISE AND FALL TIMES MEASURES FROM 10% TO 90% OF 5V, tr = tf = 5ns. 3.TIMING MEASUREMENT REFERENCE LEVEL IS VINH + V INL 2 4. IF LDAC IS ACTIVATED WHILE WR IS LOW, LDAC MUST STAY t1 t2 t7 LOW FOR t7 OR LONGER AFTER WR GOES HIGH. Figure 5. AD7245A Write Cycle Timing Diagram INTERFACE LOGIC INFORMATION—AD7248A The input loading structure on the AD7248A is configured for interfacing to microprocessors with an 8-bit wide data bus. The part contains two 12-bit latches—an input latch and a DAC latch. Only the data held in the DAC latch determines the ana- log output from the converter. The truth table for AD7248A operation is shown in Table II, while the input control logic diagram is shown in Figure 6. LDAC CSMSB CSLSB WR DAC LATCH UPPER 4 BITS OF INPUT LATCH LOWER 8 BITS OF INPUT LATCH DB7 – DB0 12 4 8 8 Figure 6. AD7248A Input Control Logic CSMSB, CSLSB and WR control the loading of data from the external data bus to the input latch. The eight data inputs on the AD7248A accept right justified data. This data is loaded to the input latch in two separate write operations. CSLSB and WR control the loading of the lower 8-bits into the 12-bit wide latch. The loading of the upper 4-bit nibble is controlled by CSMSB and WR. All control inputs are level triggered, and input data for either the lower byte or upper 4-bit nibble is latched into the input latches on the rising edge of WR (or either CSMSB or CSLSB). The order in which the data is loaded to the input latch (i.e., lower byte or upper 4-bit nibble first) is not important. |
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