ADE7912ARIZ datasheet(6/44 Pages) AD

Nome de Peças	ADE7912ARIZ

Descrição Electrónicos	3-Channel, Isolated, Sigma-Delta ADC with SPI

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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ADE7912/ADE7913

Data Sheet

Rev. 0 | Page 6 of 44

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Signal-to-Noise-and-Distortion Ratio, SINAD

72

dBFS

ADC_FREQ = 8 kHz, BW = 3300 Hz

74

dBFS

ADC_FREQ = 8 kHz, BW = 2000 Hz

77

dBFS

ADC_FREQ = 2 kHz, BW = 825 Hz

78

dBFS

ADC_FREQ = 2 kHz, BW = 500 Hz

Total Harmonic Distortion, THD

−83

dBFS

ADC_FREQ = 8 kHz, BW = 3300 Hz

−83

dBFS

ADC_FREQ = 8 kHz, BW = 2000 Hz

−85

dBFS

ADC_FREQ = 2 kHz, BW = 825 Hz

−85

dBFS

ADC_FREQ = 2 kHz, BW = 500 Hz

Spurious-Free Dynamic Range, SFDR

86

dBFS

ADC_FREQ = 8 kHz, BW = 3300 Hz

86

dBFS

ADC_FREQ = 8 kHz, BW = 2000 Hz

87

dBFS

ADC_FREQ = 2 kHz, BW = 825 Hz

87

dBFS

ADC_FREQ = 2 kHz, BW = 500 Hz

CLKIN2

All specifications for CLKIN = 4.096 MHz

Input Clock Frequency, CLKIN

3.6

4.096

4.21

MHz

CLKIN Duty Cycle

45

50

55

%

XTAL1 Logic Inputs

Input High Voltage, VINH

2.4

V

Input Low Voltage, VINL

0.8

V

XTAL1 Total Capacitance3

40

pF

XTAL2 Total Capacitance3

40

pF

CLKOUT Delay from XTAL14

100

ns

LOGIC INPUTS—MOSI, SCLK, CS

Input High Voltage, VINH

2.4

V

Input Low Voltage, VINL

0.8

V

Input Current, IIN

15

nA

Input Capacitance, CIN

10

pF

LOGIC OUTPUTS—CLKOUT/DREADY AND MISO

Output High Voltage, VOH

2.5

V

ISOURCE = 800 μA

Output Low Voltage, VOL

0.4

V

ISINK = 2 mA

POWER SUPPLY

For specified performance

VDD Pin

2.97

3.63

V

Minimum = 3.3 V − 10%; maximum = 3.3 V + 10%

IDD

12.5

19

mA

Bit 2 (PWRDWN_EN) in CONFIG register cleared to 0

2.7

3

mA

Bit 2 (PWRDWN_EN) in CONFIG register set to 1

50

μA

Bit 2 (PWRDWN_EN) in CONFIG register set to 1

and no CLKIN signal at XTAL1 pin

1 See the Terminology section for a definition of the parameters.

2 CLKIN is the internal clock of the ADE7912/ADE7913. It is the frequency at which the part is clocked at the XTAL1 pin.

3 XTAL1/XTAL2 total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance of

the ceramic capacitor connected between the pin and GND. See the ADE7912/ADE7913 Clock section for more details.

4 CLKOUT delay from XTAL1 is the delay that occurs from a high to low transition at the XTAL1 pin to a synchronous high to low transition at the CLKOUT/DREADY pin

when CLKOUT functionality is enabled.

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