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CAB4AZNRR Folha de dados(PDF) 3 Page - Texas Instruments |
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CAB4AZNRR Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 10 page CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 Table 1. TERMINAL FUNCTIONS SIGNAL TYPE DESCRIPTION GROUP NAME DCKE0/1 DRAM corresponding register function pins not associated with DODT0/1 Chip Select. DCS0_n..DCS1_ DRAM corresponding register Chip Select signals. n DRAM corresponding register Chip Select signals. These pins initiate DRAM address/command decodes, and as such exactly Input Control bus CMOS(1) VREF based DCS2_n..DCS3_ one will be LOW when a valid address/command is present n which should be re-driven. or Some of these have alternative functions: DC0..DC1 • DCS2_n ↔ DC0 • DCS3_n ↔ DC1 DC2 DRAM corresponding register Chip ID 2 signal. DRAM corresponding register inputs. In case of an ACT command some of these terminals have an alternative function: DA0..DA13, DRAM corresponding register command signals DA17 DBA0..DBA1, • DA14 ↔ DWE_n DBG0..DBG1 • DA15 ↔ DCAS_n CMOS(1) VREF based Input Address and • DA16 ↔ DRAS_n Command bus DA14..DA16 or DWE_n, DCAS_n, DRAS_n DACT_n DRAM corresponding register DACT_n signal. Differential master clock input pair to the PLL with a 10 k Ω ~ Clock inputs CK_t, CK_c CMOS differential 100 k Ω pull-down resistor. Active LOW asynchronous reset input. When LOW, it causes a Reset input DRST_n CMOS input reset of the internal latches and disables the outputs, thereby forcing the outputs to float. Input parity is received on pin DPAR and should maintain even Parity input DPAR CMOS(2) VREF based parity across the address and command inputs (see above), at the rising edge of the input clock. DRAM address parity and CRC Alert is connected to this input Error Input ERROR_IN_n CMOS input pin, which in turn is buffered and re-driven to the ALERT_n output of the register. Requires external pull-up resistor.(3) BODT Data buffer on-die termination signal. BCKE Data buffer clock enable signal for PLL power management. CMOS(3) Data buffer control Register communication bus for data buffer programming and and communication BCOM[3:0] control access. outputs BCK_t, BCK_c CMOS differential Differential clock output pair to the data buffer BVREFCA VDD/2Reference Voltage Output reference voltage for data buffer control bus receivers. (1) These receivers use VREFCA as the switching point reference. (2) These receivers use VREFCA as the switching point reference. (3) CMOS: These outputs with rail to rail signal swing and programmable impedance are optimized for memory applications to drive DRAM inputs over a terminated transmission line. Error_In_n: Internal Pull-up resistor can be turned on. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CAB4A |
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