AD7631 datasheet(5/28 Pages) AD

Nome de Peças	AD7631

Descrição Electrónicos	16-Bit, 1.5 LSB INL, 2 MSPS PulSAR ADC

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Fabricante Electrônico	AD [Analog Devices]

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AD7622

Rev. 0 | Page 5 of 28

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

CONVERSION AND RESET (Refer to Figure 31 and Figure 32)

Convert Pulse Width

t1

15

701

ns

Time Between Conversions (Warp Mode2/Normal Mode3)

t2

500/667

ns

CNVST Low to BUSY High Delay

t3

23

ns

BUSY High All Modes (Except Master Serial Read After Convert)

Warp Mode/Normal Mode

t4

360/485

ns

Aperture Delay

t5

1

ns

End of Conversion to BUSY Low Delay

t6

10

ns

Conversion Time (Warp Mode/Normal Mode)

t7

360/485

ns

Acquisition Time (Warp Mode/Normal Mode)

t8

140/182

ns

RESET Pulse Width

t9

15

ns

RESET Low to BUSY High Delay4

t38

10

ns

BUSY High Time from RESET Low4

t39

500

ns

PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 36 )

CNVST Low to Data Valid Delay (Warp Mode/Normal Mode)

t10

360/485

ns

Data Valid to BUSY Low Delay

t11

2

ns

Bus Access Request to Data Valid

t12

20

ns

Bus Relinquish Time

t13

2

15

ns

MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)

CS Low to SYNC Valid Delay

t14

10

ns

CS Low to Internal SCLK Valid Delay5

t15

10

ns

CS Low to SDOUT Delay

t16

10

ns

CNVST Low to SYNC Delay (Warp Mode/Normal Mode)

t17

15/135

ns

SYNC Asserted to SCLK First Edge Delay

t18

2

ns

Internal SCLK Period6

t19

8

20

ns

Internal SCLK High6

t20

2

ns

Internal SCLK Low6

t21

3

ns

SDOUT Valid Setup Time6

t22

1

ns

SDOUT Valid Hold Time6

t23

0

ns

SCLK Last Edge to SYNC Delay6

t24

0

ns

CS High to SYNC HI-Z

t25

10

ns

CS High to Internal SCLK HI-Z

t26

10

ns

CS High to SDOUT HI-Z

t27

10

ns

BUSY High in Master Serial Read After Convert6

t28

See Table 4

ns

CNVST Low to SYNC Asserted Delay (Warp Mode/Normal Mode)

t29

375/500

ns

SYNC Deasserted to BUSY Low Delay

t30

13

ns

SLAVE SERIAL INTERFACE MODES (Refer to Figure 40 and Figure 41)

External SCLK Setup Time

t31

5

ns

External SCLK Active Edge to SDOUT Delay

t32

1

8

ns

SDIN Setup Time

t33

5

ns

SDIN Hold Time

t34

5

ns

External SCLK Period

t35

12.5

ns

External SCLK High

t36

5

ns

External SCLK Low

t37

5

ns

See Notes on next page.

Nº de peça semelhante - AD7631

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