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AD8303AR Folha de dados(PDF) 9 Page - Analog Devices |
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AD8303AR Folha de dados(HTML) 9 Page - Analog Devices |
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9 / 16 page  AD8303 REV. 0 –9– POWER SUPPLY The very low power consumption of the AD8303 is a direct result of a circuit design optimizing the use of a CBCMOS process. By using the low power characteristics of CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, excellent analog accuracy is achieved. One advantage of the rail-to-rail output amplifiers used in the AD8303 is the wide range of usable supply voltage. The part is fully specified and tested for operation from +2.7 V to +5.5 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8303 is possible down to +2.7 V. POWER SUPPLY BYPASSING AND GROUNDING Precision analog products, such as the AD8303, require a well filtered power source. Since the AD8303 operates from a single +3 V to +5 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistances and inductances. The power supply noise generated thereby means that special care must be taken to insure that the inherent precision of the DAC is maintained. Good engineering judgment should be exercised when addressing the power supply grounding and bypassing of the AD8303. The AD8303 should be powered directly from the system power supply. This arrangement, shown in Figure 24, employs an LC filter and separate power and ground connections to isolate the analog section from the logic switching transients. Analog and digital ground pins of the AD8303 should be connected together directly at the IC package. 100µF ELECT. 10-22µF TANT. 0.1µF CER. TTL/CMOS LOGIC CIRCUITS +5V POWER SUPPLY +5V +5V RETURN FERRITE BEAD: 2 TURNS, FAIR-RITE #2677006301 Figure 24. Use Separate Traces to Reduce Power Supply Noise Whether or not a separate power supply trace is available, however, generous supply bypassing will reduce supply-line induced errors. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor is recommended in all applications (Figure 25). SDI CLK CS LDA LDB RS MSB SHDN AD8303 7 6 5 8 10 9 11 12 13 2 14 4 1 TO ANALOG GROUND VOUTA VOUTB 0.1µF 10µF +2.7V TO +5.5V AGND DGND VDD Figure 25. Recommended Supply Bypassing for the AD8303 INPUT LOGIC LEVELS All digital inputs are protected with a Zener-type ESD protection structure (Figure 26) that allows logic input voltages to exceed the VDD supply voltage. This feature can be useful if the user is driving one or more of the digital inputs with a 5 V CMOS logic input voltage level while operating the AD8303 on a +3 V power supply. If this mode of interface is used, make sure that the VOL of the 5 V CMOS meets the VIL input requirement of the AD8303 operating at 3 V. See Figure 6 for a graph for digital logic input threshold versus operating VDD supply voltage. VDD LOGIC IN GND Figure 26. Equivalent Digital Input ESD Protection For power consumption-sensitive applications, it is important to note that the internal power consumption of the AD8303 is strongly dependent on the actual logic input voltage levels present in the SDI, CLK, CS, LDA, LDB, SHDN, RS and MSB pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation which depends on the actual driving logic VOH and VOL voltage levels. Consequently, using CMOS logic versus TTL will provide minimal dissipation in the static state. |
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Descrição semelhante - AD8303AR |
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