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AD8804AR Folha de dados(PDF) 7 Page - Analog Devices |
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AD8804AR Folha de dados(HTML) 7 Page - Analog Devices |
7 / 16 page AD8802/AD8804 REV. 0 –7– PROGRAMMING THE OUTPUT VOLTAGE The output voltage range is determined by the external refer- ence connected to VREFH and VREFL pins. See Figure 16 for a simplified diagram of the equivalent DAC circuit. In the case of the AD8802 its VREFL is internally connected to GND and therefore cannot be offset. VREFH can be tied to VDD and VREFL can be tied to GND establishing a basic rail-to-rail voltage out- put programming range. Other output ranges are established by the use of different external voltage references. The general transfer equation which determines the programmed output voltage is: VO (Dx) = (Dx)/256 × (V REFH – VREFL) + VREFL Eq. 1 where Dx is the data contained in the 8-bit DACx register. MSB OX 2R R P CH N CH TO OTHER DACS R 2R 2R 2R GND VREFL LSB DAC REGISTER D6 D0 D7 VREFH ...... ... Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit For example, when VREFH = +5 V and VREFL = 0 V, the follow- ing output voltages will be generated for the following codes: Output State D VOx (VREFH = +5 V, VREFL = 0 V) 255 4.98 V Full Scale 128 2.50 V Half Scale (Midscale Reset Value) 1 0.02 V 1 LSB 0 0.00 V Zero Scale REFERENCE INPUTS (VREFH, VREFL) The reference input pins set the output voltage range of all twelve DACs. In the case of the AD8802 only the VREFH pin is available to establish a user designed full-scale output voltage. The external reference voltage can be any value between 0 and VDD but must not exceed the VDD supply voltage. The AD8804 has access to the VREFL which establishes the zero-scale output voltage, any voltage can be applied between 0 V and VDD. VREFL can be smaller or larger in voltage than VREFH since the DAC design uses fully bidirectional switches as shown in Figure 16. The input resistance to the DAC has a code dependent variation which has a nominal worst case measured at 55H, which is ap- proximately 1.2 k Ω. When V REFH is greater than VREFL, the REFL reference must be able to sink current out of the DAC ladder, while the REFH reference is sourcing current into the DAC ladder. The DAC design minimizes reference glitch cur- rent maintaining minimum interference between DAC channels during code changes. DAC OUTPUTS (O1–O12) The twelve DAC outputs present a constant output resistance of approximately 5 k Ω independent of code setting. The distribu- tion of ROUT from DAC-to-DAC typically matches within ± 1%. However device-to-device matching is process lot dependent having a ±20% variation. The change in R OUT with temperature has a 500 ppm/ °C temperature coefficient. During power shut- down all twelve outputs are open-circuited. CS CLK SDI SHDN AD8802/AD8804 D7 D0 ADDR DEC EN D11 D10 D9 D8 D7 SER REG DD0 DAC REG #1 R VDD D7 D0 DAC 12 DAC REG #12 R DAC 1 8 O1 O2 O4 O5 O6 O7 O8 O9 O10 O11 O12 VREFH GND RS (AD8802 ONLY) VREFL (AD8804 ONLY) O3 Figure 17. Block Diagram DIGITAL INTERFACING The AD8802/AD8804 contains a standard three-wire serial in- put control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Fig- ure 17 block diagram shows more detail of the internal digital circuitry. When CS is taken active low, the clock can load data into the serial register on each positive clock edge, see Table II. Table II. Input Logic Control Truth Table CS CLK Register Activity 1 X No effect. 0 P Shifts Serial Register One bit loading the next bit in from the SDI pin. P 1 Clock should be high when the CS returns to the inactive state. P = Positive Edge, X = Don’t Care. The data setup and data hold times in the specification table determine the data valid time requirements. The last 12 bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder which enables one of the twelve positive-edge triggered DAC registers, see Figure 18 detail. |
Nº de peça semelhante - AD8804AR |
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Descrição semelhante - AD8804AR |
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